[llvm] [RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). (PR #87283)

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git-clang-format --diff 4cd7bb07c7540bf83a7a60a67aa282e99461ca2f 97bf6a0ec0abe05d6411f3288b990f9e07f31130 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c37938cd95..ee83f9da49 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4628,8 +4628,8 @@ static SDValue getWideningInterleave(SDValue EvenV, SDValue OddV,
     // If OddV is undef, this is a zero extend.
     // FIXME: Not only does this optimize the code, it fixes some correctness
     // issues because MIR does not have freeze.
-    Interleaved = DAG.getNode(RISCVISD::VZEXT_VL, DL, WideContainerVT, EvenV,
-                              Mask, VL);
+    Interleaved =
+        DAG.getNode(RISCVISD::VZEXT_VL, DL, WideContainerVT, EvenV, Mask, VL);
   } else if (Subtarget.hasStdExtZvbb()) {
     // Interleaved = (OddV << VecVT.getScalarSizeInBits()) + EvenV.
     SDValue OffsetVec =

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https://github.com/llvm/llvm-project/pull/87283