[llvm] [PPC] generate stxvw4x/lxvw4x on P7 (PR #87049)

[via llvm-commits]

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@@ -17250,8 +17250,7 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
 EVT PPCTargetLowering::getOptimalMemOpType(
     const MemOp &Op, const AttributeList &FuncAttributes) const {
   if (getTargetMachine().getOptLevel() != CodeGenOptLevel::None) {
-    // We should use Altivec/VSX loads and stores when available. For unaligned
-    // addresses, unaligned VSX loads are only fast starting with the P8.
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RolandF77 wrote:

On pwr7 an lxvw4x with < 8 byte alignment will be flushed and micro-coded, and with < 4 byte alignment will be an alignment interrupt.

https://github.com/llvm/llvm-project/pull/87049