[llvm] a7206a6 - [RISCV] ReadStoreData is read later in the pipeline for SiFive7 (#86454)

[via llvm-commits]

Author: Michael Maitland
Date: 2024-04-01T09:35:42-04:00
New Revision: a7206a6fa32ada15578e3afddcc1480364c25f4c

URL: https://github.com/llvm/llvm-project/commit/a7206a6fa32ada15578e3afddcc1480364c25f4c
DIFF: https://github.com/llvm/llvm-project/commit/a7206a6fa32ada15578e3afddcc1480364c25f4c.diff

LOG: [RISCV] ReadStoreData is read later in the pipeline for SiFive7 (#86454)

Store data is read later in the pipeline, so we use
SiFive7AnyToGPRBypass to model that a store instruction can begin some
cycles before that data is ready.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 3586d235bdbbb9..54a13889ee698a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -950,7 +950,7 @@ def : InstRW<[WriteIALU], (instrs COPY)>;
 def : SiFive7AnyToGPRBypass<ReadJmp>;
 def : SiFive7AnyToGPRBypass<ReadJalr>;
 def : ReadAdvance<ReadCSR, 0>;
-def : ReadAdvance<ReadStoreData, 0>;
+def : SiFive7AnyToGPRBypass<ReadStoreData>;
 def : ReadAdvance<ReadMemBase, 0>;
 def : SiFive7AnyToGPRBypass<ReadIALU>;
 def : SiFive7AnyToGPRBypass<ReadIALU32>;