[llvm] [RISCV] Generate more W instructons (PR #87237)

[Michael Maitland via llvm-commits]

================
@@ -698,6 +700,42 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
   return MadeChange;
 }
 
+bool RISCVOptWInstrs::appendWSuffixes(MachineFunction &MF,
+                                      const RISCVInstrInfo &TII,
+                                      const RISCVSubtarget &ST,
+                                      MachineRegisterInfo &MRI) {
+  bool MadeChange = false;
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      unsigned Opc;
+      // TODO: Add more.
+      switch (MI.getOpcode()) {
+      default:
+        continue;
+      case RISCV::ADD:
+        Opc = RISCV::ADDW;
+        break;
+      case RISCV::ADDI:
+        Opc = RISCV::ADDIW;
+        break;
+      case RISCV::MUL:
+        Opc = RISCV::MULW;
+        break;
+      case RISCV::SLLI:
+        Opc = RISCV::SLLIW;
+        break;
+      }
+
+      if (hasAllWUsers(MI, ST, MRI)) {
+        MI.setDesc(TII.get(Opc));
----------------
michaelmaitland wrote:

Is it possible that `Opc` is uninitialized but used here?

https://github.com/llvm/llvm-project/pull/87237