[llvm] [CodeGen][MRI] Introduce synthetic register classes (PR #86006)

[Yashwant Singh via llvm-commits]

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@@ -257,6 +261,18 @@ class MachineRegisterInfo {
   /// Notice that it will override ant previously disabled/saved CSRs.
   void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
 
+  /// Initialize the RegClassSyntheticInfo. It sets the bit position as
+  /// exactly as the tablegened Synthetic field. Targets can later flip this
+  /// field to enable/disable the regclass whenever required.
+  void initializeRegClassSyntheticInfo();
+
+  /// Change the synthetic info for the regclass \p RC from \p Value.
+  void changeSyntheticInfoForRC(const TargetRegisterClass *RC, bool Value);
+
+  /// This function checks if \p RC is enabled or not so that it can be included
+  /// in various regclass related queries.
+  bool isEnabled(const TargetRegisterClass *RC) const;
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yashssh wrote:

Can it be better named? `isEnabled` sounds very generic to just check synthetic info. Perhaps `isSyntheticallyDisabled(RC)` ?

https://github.com/llvm/llvm-project/pull/86006