[llvm] [LegalizeDAG] Optimize CodeGen for `ISD::CTLZ_ZERO_UNDEF` (PR #83039)

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git-clang-format --diff c0febca3a64530c1cc3f117aec6a28c37114e572 5b23ff17780a815c684e87950a4fdd05a47f2718 -- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 08db2c9b07..89f4cc6726 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -665,7 +665,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
 
     // Op = Op << (sizeinbits(NVT) - sizeinbits(Old VT))
     unsigned SHLAmount = NVT.getSizeInBits() - OVT.getSizeInBits();
-    auto ShiftConst = DAG.getShiftAmountConstant(SHLAmount, Op.getValueType(), dl);
+    auto ShiftConst =
+        DAG.getShiftAmountConstant(SHLAmount, Op.getValueType(), dl);
     if (!N->isVPOpcode()) {
       Op = DAG.getNode(ISD::SHL, dl, NVT, Op, ShiftConst);
       return DAG.getNode(CtlzOpcode, dl, NVT, Op);

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https://github.com/llvm/llvm-project/pull/83039