[llvm] [RISCV] Combine (or disjoint ext, ext) -> vwadd (PR #86929)

[Luke Lau via llvm-commits]

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@@ -1394,18 +1394,15 @@ define <vscale x 1 x i64> @i1_zext(<vscale x 1 x i1> %va, <vscale x 1 x i64> %vb
 }
 
 ; %x.i32 and %y.i32 are disjoint, so DAGCombiner will combine it into an or.
-; FIXME: We should be able to recover the or into vwaddu.vv if the disjoint
-; flag is set.
+; Check that we combine disjoint ors into vwaddu.
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lukel97 wrote:

Done in 131be5de90dac9f54a8213a1aab66a75c62890ec

Interestingly enough, if the two arms of a bitwise operation are the same DAGCombiner will pull the op through the extend, so we get narrowing for free. But this prevents the current combine from converting it to a vwadd[u].vv. This might be worth adding a pattern for.

https://github.com/llvm/llvm-project/pull/86929