[llvm] [AArch64] Optimization of repeated constant loads (#51483) (PR #86249)

[via llvm-commits]

ParkHanbum wrote:

@efriedma-quic it is good for me.
what I trying to now is if we found ORR from sequence of backward then do Bit-OR when match "movn" finally.

like this. 

```
    // ValueOrder == 1 mean this is MOVZXi. 
    if (ValueOrder == 1 && DupBitSize) {
      Accumulated |= Accumulated << DupBitSize;
      DupBitSize = 0;
    } 
 ```

but this is base on assuming that "ORR(x, x, lsl 32)" was generated in pseudo-expansion. 
so, it is need verification by you experts.


https://github.com/llvm/llvm-project/pull/86249