[llvm] [RISCV] Handle fixed length vectors with exact VLEN in lowerINSERT_SUBVECTOR (PR #84107)

[Philip Reames via llvm-commits]

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@@ -2063,8 +2063,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     MVT SubVecContainerVT = SubVecVT;
     // Establish the correct scalable-vector types for any fixed-length type.
     if (SubVecVT.isFixedLengthVector()) {
-      assert(Idx == 0 && V.isUndef());
       SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT);
+      bool AlignedToVecReg = false;
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preames wrote:

Two points:
1) Naming - This doesn't appear to be checking alignment, it appears to be checking whether the fixed vector completely fills the container.
2) Variable used under assert only should be in appropriate ifndef block.  

https://github.com/llvm/llvm-project/pull/84107