[llvm] [X86] Resolve TODO: Use Tokenfactor rather than the whole chain (PR #87002)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 28 14:24:46 PDT 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/87002
>From 5c4e9e996d4c910350d7956a53b6295251d45146 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Thu, 28 Mar 2024 15:34:14 -0400
Subject: [PATCH 1/2] [X86] Resolve TODO: Use Tokenfactor rather than the whole
chain
---
llvm/lib/Target/X86/X86SelectionDAGInfo.cpp | 43 +++++++++++----------
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
index 7c630a2b0da080..0f46110f22dc93 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -67,7 +67,7 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
// The libc version is likely to be faster for these cases. It can use the
// address value and run time information about the CPU.
if (Alignment < Align(4) || !ConstantSize ||
- ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold())
+ ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold())
return SDValue();
uint64_t SizeVal = ConstantSize->getZExtValue();
@@ -128,26 +128,29 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
InGlue = Chain.getValue(1);
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
- SDValue Ops[] = { Chain, DAG.getValueType(AVT), InGlue };
- Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
-
- if (BytesLeft) {
- // Handle the last 1 - 7 bytes.
- unsigned Offset = SizeVal - BytesLeft;
- EVT AddrVT = Dst.getValueType();
- EVT SizeVT = Size.getValueType();
-
- Chain =
- DAG.getMemset(Chain, dl,
- DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
- DAG.getConstant(Offset, dl, AddrVT)),
- Val, DAG.getConstant(BytesLeft, dl, SizeVT), Alignment,
- isVolatile, AlwaysInline,
- /* isTailCall */ false, DstPtrInfo.getWithOffset(Offset));
- }
+ SDValue Ops[] = {Chain, DAG.getValueType(AVT), InGlue};
+ SDValue RepStos = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
+
+ /// RepStos can process the whole length.
+ if (BytesLeft == 0)
+ return RepStos;
- // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
- return Chain;
+ // Handle the last 1 - 7 bytes.
+ SmallVector<SDValue, 4> Results;
+ Results.push_back(RepStos);
+ unsigned Offset = SizeVal - BytesLeft;
+ EVT AddrVT = Dst.getValueType();
+ EVT SizeVT = Size.getValueType();
+
+ Results.push_back(
+ DAG.getMemset(Chain, dl,
+ DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
+ DAG.getConstant(Offset, dl, AddrVT)),
+ Val, DAG.getConstant(BytesLeft, dl, SizeVT), Alignment,
+ isVolatile, AlwaysInline,
+ /* isTailCall */ false, DstPtrInfo.getWithOffset(Offset)));
+
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
}
/// Emit a single REP MOVS{B,W,D,Q} instruction.
>From 0596ef7106328fe7219aa946ade85b730e47a11b Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Thu, 28 Mar 2024 17:23:10 -0400
Subject: [PATCH 2/2] Update X86SelectionDAGInfo.cpp
---
llvm/lib/Target/X86/X86SelectionDAGInfo.cpp | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
index 0f46110f22dc93..8b2d6316560863 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -48,19 +48,18 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo) const {
+ // If to a segment-relative address space, use the default lowering.
+ if (DstPtrInfo.getAddrSpace() >= 256)
+ return SDValue();
+
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
const X86Subtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<X86Subtarget>();
-#ifndef NDEBUG
// If the base register might conflict with our physical registers, bail out.
const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
X86::ECX, X86::EAX, X86::EDI};
- assert(!isBaseRegConflictPossible(DAG, ClobberSet));
-#endif
-
- // If to a segment-relative address space, use the default lowering.
- if (DstPtrInfo.getAddrSpace() >= 256)
+ if (isBaseRegConflictPossible(DAG, ClobberSet))
return SDValue();
// If not DWORD aligned or size is more than the threshold, call the library.
More information about the llvm-commits
mailing list