[llvm] [SystemZ] Eliminate call sequence instructions early. (PR #77812)

[Jonas Paulsson via llvm-commits]

JonPsson1 wrote:

ok - patch updated to remove the MI pseudo early. Some test changes where one was a bit of an example of where the mi-scheduler actually does mess things up a bit:
```

0B      bb.0 (%ir-block.0):
          liveins: $r1d, $f0d, $r5d
16B       %2:addr64bit = COPY $r5d
32B       %1:fp64bit = COPY $f0d
48B       %0:gr64bit = COPY $r1d
64B       %3:gr64bit = LGDR %1:fp64bit
80B       %4:gr64bit = ADA_ENTRY_VALUE target-flags(<unknown>) @pass_vararg3, %2:addr64bit, 8, implicit-def dead $cc :: (dereferenceable invariant load (s64))
96B       %6:gr64bit = ADA_ENTRY_VALUE target-flags(<unknown>) @pass_vararg3, %2:addr64bit, 0, implicit-def dead $cc :: (dereferenceable invariant load (s64))
112B      $r6d = COPY %4:gr64bit
128B      $r1d = COPY %3:gr64bit
144B      $r2d = COPY %0:gr64bit
160B      $r5d = COPY %6:gr64bit
176B      CallBASR_XPLINK64 killed $r6d, $r1d, killed $r2d, $r5d, <regmask $f8d $f9d $f10d $f11d $f12d $f13d $f14d $f15d $f8q $f9q $f12q $f13q $f8s $f9s $f10s $f11s $f12s $f13s $f14s $f15s $r8d $r9d $r10d $r11d 
$r12d $r13d $r14d $r15d $r8h $r9h $r10h $r11h $r12h and 15 more...>, implicit-def dead $r7d, implicit-def dead $cc, implicit $fpc, implicit-def $r3d
192B      %8:gr64bit = COPY killed $r3d
208B      $r3d = COPY %8:gr64bit
224B      Return_XPLINK implicit killed $r3d

# End machine code for function call_vararg_both0.

# *** IR Dump After Machine Instruction Scheduler (machine-scheduler) ***:
# Machine code for function call_vararg_both0: NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $r1d in %0, $f0d in %1, $r5d in %2

0B      bb.0 (%ir-block.0):
          liveins: $r1d, $f0d, $r5d
16B       %2:addr64bit = COPY $r5d
80B       %4:gr64bit = ADA_ENTRY_VALUE target-flags(<unknown>) @pass_vararg3, %2:addr64bit, 8, implicit-def dead $cc :: (dereferenceable invariant load (s64))
96B       %6:gr64bit = ADA_ENTRY_VALUE target-flags(<unknown>) @pass_vararg3, %2:addr64bit, 0, implicit-def dead $cc :: (dereferenceable invariant load (s64))
104B      %1:fp64bit = COPY $f0d
112B      %3:gr64bit = LGDR %1:fp64bit
120B      %0:gr64bit = COPY $r1d
128B      $r6d = COPY %4:gr64bit
136B      $r1d = COPY %3:gr64bit
144B      $r2d = COPY %0:gr64bit
160B      $r5d = COPY %6:gr64bit
176B      CallBASR_XPLINK64 killed $r6d, $r1d, killed $r2d, $r5d, <regmask $f8d $f9d $f10d $f11d $f12d $f13d $f14d $f15d $f8q $f9q $f12q $f13q $f8s $f9s $f10s $f11s $f12s $f13s $f14s $f15s $r8d $r9d $r10d $r11d 
```

The LGDR was in the presence of ADJCALLSTACKDOWN below it, and is moved just above it by the mi-scheduler. For some reason, here without the ADJCALLSTACKDOWN, it is also moved above the COPY from $r1d, which is unfortunate as that causes an overlap of %3 which is to be COPY:ed to the same register.

I don't think there is any "tracking" of which vreg ranges go to/from which physreg and with that avoid unnecessary overlaps like this. Maybe this is rare so it's not worth the effort? Probably not a quick thing to fix, but this is a good example of this problem. Maybe mark the test with a TODO if this is acceptable for now?




https://github.com/llvm/llvm-project/pull/77812