[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Matt Arsenault via llvm-commits]

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@@ -63,6 +63,12 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
                         const CCValAssign &VA) override {
+    if (VA.getLocVT() == MVT::i1 &&
+        MIRBuilder.getMF().getSubtarget<GCNSubtarget>().isWave64()) {
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arsenm wrote:

The wave32 and wave64 paths shouldn't diverge. The special case is i1, independent of the wavesize 

https://github.com/llvm/llvm-project/pull/72461