[llvm] [ARM] r11 is reserved when using -mframe-chain=aapcs (PR #86951)

[via llvm-commits]

https://github.com/ostannard created https://github.com/llvm/llvm-project/pull/86951

When using the -mframe-chain=aapcs or -mframe-chain=aapcs-leaf options, we cannot use r11 as an allocatable register, even if -fomit-frame-pointer is also used. This is so that r11 will always point to a valid frame record, even if we don't create one in every function.

>From 8d9a8e14483570bcb3c205671724e4fc72407292 Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Thu, 28 Mar 2024 13:34:43 +0000
Subject: [PATCH] [ARM] r11 is reserved when using -mframe-chain=aapcs

When using the -mframe-chain=aapcs or -mframe-chain=aapcs-leaf options,
we cannot use r11 as an allocatable register, even if
-fomit-frame-pointer is also used. This is so that r11 will always point
to a valid frame record, even if we don't create one in every function.
---
 llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp   |  2 +-
 .../CodeGen/ARM/frame-pointer-reserved.ll     | 23 +++++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/ARM/frame-pointer-reserved.ll

diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 9adf758b46c481..c149db3144c7c2 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -207,7 +207,7 @@ getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, ARM::PC);
   markSuperRegs(Reserved, ARM::FPSCR);
   markSuperRegs(Reserved, ARM::APSR_NZCV);
-  if (TFI->hasFP(MF))
+  if (TFI->isFPReserved(MF))
     markSuperRegs(Reserved, STI.getFramePointerReg());
   if (hasBasePointer(MF))
     markSuperRegs(Reserved, BasePtr);
diff --git a/llvm/test/CodeGen/ARM/frame-pointer-reserved.ll b/llvm/test/CodeGen/ARM/frame-pointer-reserved.ll
new file mode 100644
index 00000000000000..d1a50c25432abf
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/frame-pointer-reserved.ll
@@ -0,0 +1,23 @@
+; RUN: llc -mtriple armv7a-none-eabi < %s --frame-pointer=all  | FileCheck %s --check-prefixes CHECK,FPALL-ARM
+; RUN: llc -mtriple armv6m-none-eabi < %s --frame-pointer=all  | FileCheck %s --check-prefixes CHECK,FPALL-THUMB1
+; RUN: llc -mtriple armv7m-none-eabi < %s --frame-pointer=all  | FileCheck %s --check-prefixes CHECK,FPALL-THUMB2
+; RUN: llc -mtriple armv7a-none-eabi < %s --frame-pointer=none | FileCheck %s --check-prefixes CHECK,FPNONE
+; RUN: llc -mtriple armv6m-none-eabi < %s --frame-pointer=none | FileCheck %s --check-prefixes CHECK,FPNONE
+; RUN: llc -mtriple armv7m-none-eabi < %s --frame-pointer=none | FileCheck %s --check-prefixes CHECK,FPNONE
+
+; When the AAPCS frame chain is enabled, check that r11 is either used as a
+; frame pointer, which must point to an ABI-compatible frame record, or not
+; used at all, so that it continues to point to a valid frame record for the
+; calling function.
+
+define i32 @foo(i32 %a) "target-features"="+aapcs-frame-chain" {
+; CHECK-LABEL: foo:
+; FPALL-ARM: add r11, sp, 
+; FPALL-THUMB1: mov r11, sp
+; FPALL-THUMB2: add.w r11, sp, 
+; FPNONE-NOT: r11
+entry:
+  tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r12},~{lr}"()
+  ret i32 %a
+}
+