[llvm] [ARM] Add reference to `ARMAsmParser` in `ARMOperand` (PR #86110)

Simon Tatham via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 28 04:38:05 PDT 2024


================
@@ -3378,7 +3387,21 @@ class ARMOperand : public MCParsedAsmOperand {
 
   void addVecListOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
-    Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
+
+    if (isAnyVectorList())
+      Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
+    else if (isDReg() && !Parser->hasMVE()) {
+      Inst.addOperand(MCOperand::createReg(Reg.RegNum));
+    } else if (isQReg() && !Parser->hasMVE()) {
+      auto DPair = Parser->getDRegFromQReg(Reg.RegNum);
+      DPair = Parser->getMRI()->getMatchingSuperReg(
+          DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
+      Inst.addOperand(MCOperand::createReg(DPair));
----------------
statham-arm wrote:

I must admit that I haven't fully followed the logic of how these various cases match up to the code you've removed from the matcher. But structurally it's surely an improvement to avoid that uncontrolled mutation, and if this gets through the full test suite then I'm happy!

https://github.com/llvm/llvm-project/pull/86110


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