[llvm] Support replacing `add rd, Zero, Zero` with `c.li rd, 0` (PR #86937)

[Mark Goncharov via llvm-commits]

https://github.com/mga-sc created https://github.com/llvm/llvm-project/pull/86937

None

>From 635929ca60c5c83fb44c8c9e6e3945b4f031cefb Mon Sep 17 00:00:00 2001
From: Mark Goncharov <mark.goncharov at syntacore.com>
Date: Thu, 28 Mar 2024 12:49:41 +0300
Subject: [PATCH] Support replacing `add rd, Zero, Zero` with `c.li rd, 0`

---
 llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 2 ++
 llvm/test/CodeGen/RISCV/compress.ll      | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 18d38348f7214f..1561956950e2c4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -996,6 +996,8 @@ let Predicates = [HasStdExtCOrZca] in {
 def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
                   (C_JR GPRNoX0:$rs1)>;
 let isCompressOnly = true in {
+def : CompressPat<(ADD GPRNoX0:$rs1, X0, X0),
+                  (C_LI GPRNoX0:$rs1, 0)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, X0, GPRNoX0:$rs2),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),
diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll
index 8fb520fac41ee0..47744492aaab6f 100644
--- a/llvm/test/CodeGen/RISCV/compress.ll
+++ b/llvm/test/CodeGen/RISCV/compress.ll
@@ -174,3 +174,12 @@ define i32 @neg_i32_hi20_only() #0 {
 ; RV32IC-NEXT:  c.jr ra
   ret i32 -65536
 }
+
+define i32 @add_zero_zero_to_li() #0 {
+; RV32IC-LABEL: <add_zero_zero_to_li>:
+; RV32IC:       c.li a0, 0
+; RV32IC:       c.jr ra
+entry:
+  %0 = tail call i32 asm "add $0, zero, zero", "=r"()
+  ret i32 %0
+}