[llvm] [X86][AVX] Fix handling of out-of-bounds shift amounts in AVX2 vector logical shift nodes #83840 (PR #86922)

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git-clang-format --diff 864a88610594d8244e007e9a6e563e2c0f16d1cd eaaa9b57b5749f9fbb31b2564def7c7587604590 -- llvm/lib/Target/X86/X86ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d36b96bd66..bb973c5997 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45569,13 +45569,15 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
   if (N->getOpcode() == ISD::VSELECT && LHS.getOpcode() == ISD::SRL &&
       supportedVectorVarShift(VT, Subtarget, ISD::SRL)) {
     APInt SV;
-    if (Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == LHS.getOperand(1) &&
+    if (Cond.getOpcode() == ISD::SETCC &&
+        Cond.getOperand(0) == LHS.getOperand(1) &&
         cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETULT &&
         ISD::isConstantSplatVector(Cond.getOperand(1).getNode(), SV) &&
         ISD::isConstantSplatVectorAllZeros(RHS.getNode()) &&
         SV == VT.getScalarSizeInBits()) {
       SDLoc DL(LHS);
-      return DAG.getNode(X86ISD::VSRLV, DL, LHS->getVTList(), LHS.getOperand(0), LHS.getOperand(1));
+      return DAG.getNode(X86ISD::VSRLV, DL, LHS->getVTList(), LHS.getOperand(0),
+                         LHS.getOperand(1));
     }
   }
 

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https://github.com/llvm/llvm-project/pull/86922