[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michal Terepeta via llvm-commits]

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@@ -307,44 +307,68 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX
+        : VPseudoVC_X<OpClass, RS1Class>,
+          Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
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michalt wrote:

No, that's probably just me not understanding LLVM's scheduling well enough... Most of the VCIX instructions do indeed read data (mostly vector registers, but in a few cases also scalar ones). I guess that would need the `LMULSchedReads` (similar to the `LMULSchedWrites`)? (and then `LMULReadAdvance`?)

https://github.com/llvm/llvm-project/pull/86093