[llvm] [InstCombine] Reduce nested logical operator if poison is implied (PR #86823)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 27 09:10:52 PDT 2024
https://github.com/XChy created https://github.com/llvm/llvm-project/pull/86823
Fixes #76623
Alive2 proof: https://alive2.llvm.org/ce/z/gX6znJ (I'm not sure how to write a proof for such transform, maybe there are mistakes)
In most cases, `icmp(a, C1) && (other_cond && icmp(a, C2))` will be reduced to `icmp(a, C1) && (other_cond && icmp(a, C2))`, since latter icmp always implies the poison of the former. After reduction, it's easier to simplify the icmp chain.
Similarly, we do the same thing for `(A && B) && C --> A && (B & C)`. Maybe we could constraint such reduction only on icmps if there is regression in benchmarks.
>From 23ad457fa3ee4c05e69187ae2d5de12f8a41d506 Mon Sep 17 00:00:00 2001
From: XChy <xxs_chy at outlook.com>
Date: Wed, 27 Mar 2024 23:24:30 +0800
Subject: [PATCH 1/2] [InstCombine][NFC] Precommit tests
---
.../Transforms/InstCombine/and-or-icmps.ll | 68 +++++++
.../Transforms/InstCombine/logical-select.ll | 166 ++++++++++++++++++
2 files changed, 234 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
index c8d348df5f427c..97b95d5a8703ed 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -3038,3 +3038,71 @@ define i32 @icmp_slt_0_or_icmp_add_1_sge_100_i32_fail(i32 %x) {
%D = or i32 %C, %B
ret i32 %D
}
+
+define i1 @logical_and_icmps1(i32 %a, i1 %other_cond) {
+; CHECK-LABEL: @logical_and_icmps1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[RET1:%.*]] = select i1 [[RET:%.*]], i1 [[CMP2]], i1 false
+; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i32 [[A]], 10086
+; CHECK-NEXT: [[RET2:%.*]] = select i1 [[RET1]], i1 [[CMP3]], i1 false
+; CHECK-NEXT: ret i1 [[RET2]]
+;
+entry:
+ %cmp1 = icmp sgt i32 %a, -1
+ %logical_and = select i1 %other_cond, i1 %cmp1, i1 false
+ %cmp2 = icmp slt i32 %a, 10086
+ %ret = select i1 %logical_and, i1 %cmp2, i1 false
+ ret i1 %ret
+}
+
+define i1 @logical_and_icmps2(i32 %a, i1 %other_cond) {
+; CHECK-LABEL: @logical_and_icmps2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[LOGICAL_AND:%.*]] = select i1 [[OTHER_COND:%.*]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[A]], 10086
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[LOGICAL_AND]], i1 [[CMP2]], i1 false
+; CHECK-NEXT: ret i1 [[RET]]
+;
+entry:
+ %cmp1 = icmp slt i32 %a, -1
+ %logical_and = select i1 %other_cond, i1 %cmp1, i1 false
+ %cmp2 = icmp eq i32 %a, 10086
+ %ret = select i1 %logical_and, i1 %cmp2, i1 false
+ ret i1 %ret
+}
+
+define <4 x i1> @logical_and_icmps_vec1(<4 x i32> %a, <4 x i1> %other_cond) {
+; CHECK-LABEL: @logical_and_icmps_vec1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt <4 x i32> [[A:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[RET1:%.*]] = select <4 x i1> [[RET:%.*]], <4 x i1> [[CMP2]], <4 x i1> zeroinitializer
+; CHECK-NEXT: [[CMP3:%.*]] = icmp slt <4 x i32> [[A]], <i32 10086, i32 10086, i32 10086, i32 10086>
+; CHECK-NEXT: [[RET2:%.*]] = select <4 x i1> [[RET1]], <4 x i1> [[CMP3]], <4 x i1> zeroinitializer
+; CHECK-NEXT: ret <4 x i1> [[RET2]]
+;
+entry:
+ %cmp1 = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1 >
+ %logical_and = select <4 x i1> %other_cond, <4 x i1> %cmp1, <4 x i1> zeroinitializer
+ %cmp2 = icmp slt <4 x i32> %a, <i32 10086, i32 10086, i32 10086, i32 10086 >
+ %ret = select <4 x i1> %logical_and, <4 x i1> %cmp2, <4 x i1> zeroinitializer
+ ret <4 x i1> %ret
+}
+
+define i1 @logical_and_icmps_fail1(i32 %a, i32 %b, i1 %other_cond) {
+; CHECK-LABEL: @logical_and_icmps_fail1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[LOGICAL_AND:%.*]] = select i1 [[OTHER_COND:%.*]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[LOGICAL_AND]], i1 [[CMP2]], i1 false
+; CHECK-NEXT: ret i1 [[RET]]
+;
+entry:
+ %cmp1 = icmp sgt i32 %a, -1
+ %logical_and = select i1 %other_cond, i1 %cmp1, i1 false
+ %cmp2 = icmp slt i32 %a, %b
+ %ret = select i1 %logical_and, i1 %cmp2, i1 false
+ ret i1 %ret
+}
diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll
index f0ea09c0884744..e41d49ba577f90 100644
--- a/llvm/test/Transforms/InstCombine/logical-select.ll
+++ b/llvm/test/Transforms/InstCombine/logical-select.ll
@@ -1303,3 +1303,169 @@ define i1 @logical_or_and_with_common_not_op_variant5(i1 %a) {
%or = select i1 %a, i1 true, i1 %and
ret i1 %or
}
+
+define i1 @reduce_logical_and1(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @reduce_logical_and1(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, %b
+ %and1 = select i1 %a, i1 %cmp1, i1 false
+ %and2 = select i1 %and1, i1 %cmp, i1 false
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_and2(i1 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: @reduce_logical_and2(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = xor i1 [[C:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1:%.*]], i1 [[CMP]], i1 false
+; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2]], i1 [[B]], i1 false
+; CHECK-NEXT: ret i1 [[AND3]]
+;
+bb:
+ %or = xor i1 %c, %b
+ %and1 = select i1 %a, i1 %or, i1 false
+ %and2 = select i1 %and1, i1 %b, i1 false
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_and3(i1 %a, i32 %b, i32 noundef %c) {
+; CHECK-LABEL: @reduce_logical_and3(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP]], i1 false
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, %b
+ %and1 = select i1 %a, i1 %cmp, i1 false
+ %and2 = select i1 %and1, i1 %cmp1, i1 false
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_or1(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @reduce_logical_or1(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP]]
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, %b
+ %and1 = select i1 %a, i1 true, i1 %cmp1
+ %and2 = select i1 %and1, i1 true, i1 %cmp
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_or2(i1 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: @reduce_logical_or2(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = xor i1 [[C:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1:%.*]], i1 true, i1 [[CMP]]
+; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2]], i1 true, i1 [[B]]
+; CHECK-NEXT: ret i1 [[AND3]]
+;
+bb:
+ %or = xor i1 %c, %b
+ %and1 = select i1 %a, i1 true, i1 %or
+ %and2 = select i1 %and1, i1 true, i1 %b
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_or3(i1 %a, i32 %b, i32 noundef %c) {
+; CHECK-LABEL: @reduce_logical_or3(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, %b
+ %and1 = select i1 %a, i1 true, i1 %cmp
+ %and2 = select i1 %and1, i1 true, i1 %cmp1
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_and_fail1(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @reduce_logical_and_fail1(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP]], i1 false
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, %b
+ %and1 = select i1 %a, i1 %cmp, i1 false
+ %and2 = select i1 %and1, i1 %cmp1, i1 false
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_and_fail2(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @reduce_logical_and_fail2(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], 7
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP]], i1 false
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, 7
+ %and1 = select i1 %a, i1 %cmp, i1 false
+ %and2 = select i1 %and1, i1 %cmp1, i1 false
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_or_fail1(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @reduce_logical_or_fail1(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, %b
+ %and1 = select i1 %a, i1 true, i1 %cmp
+ %and2 = select i1 %and1, i1 true, i1 %cmp1
+ ret i1 %and2
+}
+
+define i1 @reduce_logical_or_fail2(i1 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: @reduce_logical_or_fail2(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], 7
+; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT: ret i1 [[AND2]]
+;
+bb:
+ %cmp = icmp slt i32 %b, 6
+ %cmp1 = icmp sgt i32 %c, 7
+ %and1 = select i1 %a, i1 true, i1 %cmp
+ %and2 = select i1 %and1, i1 true, i1 %cmp1
+ ret i1 %and2
+}
>From 8a8c0081f25632a6de573701756ddca1fcc8c149 Mon Sep 17 00:00:00 2001
From: XChy <xxs_chy at outlook.com>
Date: Wed, 27 Mar 2024 23:07:24 +0800
Subject: [PATCH 2/2] [InstCombine] Reduce nested logical operator if poison is
implied
---
.../InstCombine/InstCombineSelect.cpp | 16 +++++++++++
.../Transforms/InstCombine/and-or-icmps.ll | 18 ++++---------
.../Transforms/InstCombine/logical-select.ll | 27 +++++++++----------
3 files changed, 34 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 9ab2bd8f70aa15..211c116f5a347d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -2985,6 +2985,14 @@ Instruction *InstCombinerImpl::foldSelectOfBools(SelectInst &SI) {
return BinaryOperator::CreateOr(CondVal, FalseVal);
}
+ if (match(CondVal, m_LogicalOr(m_Value(A), m_Value(B))) &&
+ isa<SelectInst>(CondVal) && impliesPoison(FalseVal, B)) {
+ // (A || B) || C --> A || (B | C)
+ return replaceInstUsesWith(
+ SI, Builder.CreateLogicalOp(Instruction::Or, A,
+ Builder.CreateOr(B, FalseVal)));
+ }
+
if (auto *LHS = dyn_cast<FCmpInst>(CondVal))
if (auto *RHS = dyn_cast<FCmpInst>(FalseVal))
if (Value *V = foldLogicOfFCmps(LHS, RHS, /*IsAnd*/ false,
@@ -3026,6 +3034,14 @@ Instruction *InstCombinerImpl::foldSelectOfBools(SelectInst &SI) {
return BinaryOperator::CreateAnd(CondVal, TrueVal);
}
+ if (match(CondVal, m_LogicalAnd(m_Value(A), m_Value(B))) &&
+ isa<SelectInst>(CondVal) && impliesPoison(TrueVal, B)) {
+ // (A && B) && C --> A && (B & C)
+ return replaceInstUsesWith(
+ SI, Builder.CreateLogicalOp(Instruction::And, A,
+ Builder.CreateAnd(B, TrueVal)));
+ }
+
if (auto *LHS = dyn_cast<FCmpInst>(CondVal))
if (auto *RHS = dyn_cast<FCmpInst>(TrueVal))
if (Value *V = foldLogicOfFCmps(LHS, RHS, /*IsAnd*/ true,
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
index 97b95d5a8703ed..63b11d0c0bc086 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -3042,10 +3042,8 @@ define i32 @icmp_slt_0_or_icmp_add_1_sge_100_i32_fail(i32 %x) {
define i1 @logical_and_icmps1(i32 %a, i1 %other_cond) {
; CHECK-LABEL: @logical_and_icmps1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[A:%.*]], -1
-; CHECK-NEXT: [[RET1:%.*]] = select i1 [[RET:%.*]], i1 [[CMP2]], i1 false
-; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i32 [[A]], 10086
-; CHECK-NEXT: [[RET2:%.*]] = select i1 [[RET1]], i1 [[CMP3]], i1 false
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i32 [[A:%.*]], 10086
+; CHECK-NEXT: [[RET2:%.*]] = select i1 [[RET1:%.*]], i1 [[CMP3]], i1 false
; CHECK-NEXT: ret i1 [[RET2]]
;
entry:
@@ -3059,11 +3057,7 @@ entry:
define i1 @logical_and_icmps2(i32 %a, i1 %other_cond) {
; CHECK-LABEL: @logical_and_icmps2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], -1
-; CHECK-NEXT: [[LOGICAL_AND:%.*]] = select i1 [[OTHER_COND:%.*]], i1 [[CMP1]], i1 false
-; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[A]], 10086
-; CHECK-NEXT: [[RET:%.*]] = select i1 [[LOGICAL_AND]], i1 [[CMP2]], i1 false
-; CHECK-NEXT: ret i1 [[RET]]
+; CHECK-NEXT: ret i1 false
;
entry:
%cmp1 = icmp slt i32 %a, -1
@@ -3076,10 +3070,8 @@ entry:
define <4 x i1> @logical_and_icmps_vec1(<4 x i32> %a, <4 x i1> %other_cond) {
; CHECK-LABEL: @logical_and_icmps_vec1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt <4 x i32> [[A:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[RET1:%.*]] = select <4 x i1> [[RET:%.*]], <4 x i1> [[CMP2]], <4 x i1> zeroinitializer
-; CHECK-NEXT: [[CMP3:%.*]] = icmp slt <4 x i32> [[A]], <i32 10086, i32 10086, i32 10086, i32 10086>
-; CHECK-NEXT: [[RET2:%.*]] = select <4 x i1> [[RET1]], <4 x i1> [[CMP3]], <4 x i1> zeroinitializer
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ult <4 x i32> [[A:%.*]], <i32 10086, i32 10086, i32 10086, i32 10086>
+; CHECK-NEXT: [[RET2:%.*]] = select <4 x i1> [[RET1:%.*]], <4 x i1> [[CMP3]], <4 x i1> zeroinitializer
; CHECK-NEXT: ret <4 x i1> [[RET2]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll
index e41d49ba577f90..834773544a5546 100644
--- a/llvm/test/Transforms/InstCombine/logical-select.ll
+++ b/llvm/test/Transforms/InstCombine/logical-select.ll
@@ -1309,8 +1309,8 @@ define i1 @reduce_logical_and1(i1 %a, i32 %b, i32 %c) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
-; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP1]], i1 false
-; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP]], i1 false
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[CMP1]], [[CMP]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 [[TMP0]], i1 false
; CHECK-NEXT: ret i1 [[AND2]]
;
bb:
@@ -1324,9 +1324,9 @@ bb:
define i1 @reduce_logical_and2(i1 %a, i1 %b, i1 %c) {
; CHECK-LABEL: @reduce_logical_and2(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[CMP:%.*]] = xor i1 [[C:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1:%.*]], i1 [[CMP]], i1 false
-; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2]], i1 [[B]], i1 false
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT: [[B:%.*]] = and i1 [[TMP0]], [[B1:%.*]]
+; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2:%.*]], i1 [[B]], i1 false
; CHECK-NEXT: ret i1 [[AND3]]
;
bb:
@@ -1341,8 +1341,8 @@ define i1 @reduce_logical_and3(i1 %a, i32 %b, i32 noundef %c) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
-; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP]], i1 false
-; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP1]], i1 false
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[CMP]], [[CMP1]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 [[TMP0]], i1 false
; CHECK-NEXT: ret i1 [[AND2]]
;
bb:
@@ -1358,8 +1358,8 @@ define i1 @reduce_logical_or1(i1 %a, i32 %b, i32 %c) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
-; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP1]]
-; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP]]
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[CMP1]], [[CMP]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[TMP0]]
; CHECK-NEXT: ret i1 [[AND2]]
;
bb:
@@ -1373,9 +1373,8 @@ bb:
define i1 @reduce_logical_or2(i1 %a, i1 %b, i1 %c) {
; CHECK-LABEL: @reduce_logical_or2(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[CMP:%.*]] = xor i1 [[C:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1:%.*]], i1 true, i1 [[CMP]]
-; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2]], i1 true, i1 [[B]]
+; CHECK-NEXT: [[B:%.*]] = or i1 [[C:%.*]], [[B1:%.*]]
+; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2:%.*]], i1 true, i1 [[B]]
; CHECK-NEXT: ret i1 [[AND3]]
;
bb:
@@ -1390,8 +1389,8 @@ define i1 @reduce_logical_or3(i1 %a, i32 %b, i32 noundef %c) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6
; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]]
-; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP]]
-; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[CMP]], [[CMP1]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[TMP0]]
; CHECK-NEXT: ret i1 [[AND2]]
;
bb:
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