[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[via llvm-commits]

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@@ -2859,7 +2863,11 @@ static void computeCalleeSaveRegisterPairs(
           RPI.Reg2 = NextReg;
         break;
       case RegPairInfo::PPR:
+        break;
       case RegPairInfo::ZPR:
+        if (Subtarget.hasSVE2p1() || Subtarget.hasSME2())
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CarolineConcatto wrote:

I can, but it woyld be use only once if it checks:
  if sve2.1 or sme2 
  if R1 and R2 are consecutive 
  if R1 and R2 are  ZRegs.

https://github.com/llvm/llvm-project/pull/77665