[llvm] [llvm][CodeGen] Added a check in CodeGenPrepare::optimizeSwitchType (PR #83322)
Panagiotis K via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 26 21:01:20 PDT 2024
https://github.com/karouzakisp updated https://github.com/llvm/llvm-project/pull/83322
>From 7dd76333651ef0f14a6d9c08abe082fdeae2450e Mon Sep 17 00:00:00 2001
From: Panagiotis K <karouzakisp at gmail.com>
Date: Thu, 29 Feb 2024 00:02:05 +0000
Subject: [PATCH] [llvm][CodeGen] Added a check in
CodeGenPrepare::OptimizeSwitchType, so that if we have more SExt
Users than ZExt Users we use SExt instead of a ZExt in the Switch
Condition because that creates a redundant instruction.
---
llvm/lib/CodeGen/CodeGenPrepare.cpp | 34 +++++-
llvm/test/CodeGen/RISCV/opt-switch-type.ll | 128 +++++++++++++++++++++
llvm/test/CodeGen/RISCV/switch-width.ll | 107 +++++++++++++++--
3 files changed, 251 insertions(+), 18 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/opt-switch-type.ll
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index feefe87f406365..0070d0747dee01 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -7387,17 +7387,39 @@ bool CodeGenPrepare::optimizeSwitchType(SwitchInst *SI) {
// attribute. In that case, we can avoid an unnecessary mask/extension by
// matching the argument extension instead.
Instruction::CastOps ExtType = Instruction::ZExt;
- // Some targets prefer SExt over ZExt.
- if (TLI->isSExtCheaperThanZExt(OldVT, RegType))
- ExtType = Instruction::SExt;
-
+
+ unsigned SExtUsers = 0;
+ unsigned ZExtUsers = 0;
if (auto *Arg = dyn_cast<Argument>(Cond)) {
if (Arg->hasSExtAttr())
- ExtType = Instruction::SExt;
+ SExtUsers++;
if (Arg->hasZExtAttr())
- ExtType = Instruction::ZExt;
+ ZExtUsers++;
+ }
+ for (auto U : Cond->users()) {
+ if (isa<SExtInst>(U) ) {
+ SExtUsers++;
+ }else if(isa<ZExtInst>(U)){
+ ZExtUsers++;
+ }
+ else if(auto *IC = dyn_cast<ICmpInst>(U)){
+ if(IC->isSigned()){
+ SExtUsers++;
+ }else if(IC->isUnsigned()){
+ ZExtUsers++;
+ }
+ }
+ }
+ if (SExtUsers > ZExtUsers) {
+ ExtType = Instruction::SExt;
+ }else{
+ ExtType = Instruction::ZExt;
}
+ // Some targets prefer SExt over ZExt.
+ if (TLI->isSExtCheaperThanZExt(OldVT, RegType))
+ ExtType = Instruction::SExt;
+
auto *ExtInst = CastInst::Create(ExtType, Cond, NewType);
ExtInst->insertBefore(SI);
ExtInst->setDebugLoc(SI->getDebugLoc());
diff --git a/llvm/test/CodeGen/RISCV/opt-switch-type.ll b/llvm/test/CodeGen/RISCV/opt-switch-type.ll
new file mode 100644
index 00000000000000..c2810e972997e2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/opt-switch-type.ll
@@ -0,0 +1,128 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+define dso_local void @test_switch_2_users(ptr nocapture noundef readonly %x) local_unnamed_addr {
+; RV64I-LABEL: test_switch_2_users:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: li a1, 16
+; RV64I-NEXT: blt a0, a1, .LBB0_5
+; RV64I-NEXT: # %bb.1: # %if.then
+; RV64I-NEXT: addi a1, a0, -17
+; RV64I-NEXT: li a2, 2
+; RV64I-NEXT: bgeu a1, a2, .LBB0_3
+; RV64I-NEXT: # %bb.2: # %sw.bb3
+; RV64I-NEXT: call foo2
+; RV64I-NEXT: j .LBB0_5
+; RV64I-NEXT: .LBB0_3: # %if.then
+; RV64I-NEXT: li a1, 16
+; RV64I-NEXT: bne a0, a1, .LBB0_5
+; RV64I-NEXT: # %bb.4: # %sw.bb
+; RV64I-NEXT: call foo1
+; RV64I-NEXT: .LBB0_5: # %if.end
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: tail foo3
+entry:
+ %0 = load i16, ptr %x, align 2
+ %cmp = icmp sgt i16 %0, 15
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ switch i16 %0, label %if.end [
+ i16 16, label %sw.bb
+ i16 17, label %sw.bb3
+ i16 18, label %sw.bb3
+ ]
+
+sw.bb:
+ tail call void @foo1() #2
+ br label %if.end
+
+sw.bb3:
+ tail call void @foo2() #2
+ br label %if.end
+
+if.end:
+ tail call void @foo3() #2
+ ret void
+}
+
+declare void @foo1(...) local_unnamed_addr #1
+
+declare void @foo2(...) local_unnamed_addr #1
+
+declare void @foo3(...) local_unnamed_addr #1
+
+define dso_local void @foo(ptr nocapture noundef readonly %x) local_unnamed_addr {
+; RV64I-LABEL: foo:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: li a1, 16
+; RV64I-NEXT: blt a0, a1, .LBB1_6
+; RV64I-NEXT: # %bb.1: # %entry
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -4
+; RV64I-NEXT: and a1, a0, a1
+; RV64I-NEXT: li a2, 4
+; RV64I-NEXT: bne a1, a2, .LBB1_6
+; RV64I-NEXT: # %bb.2: # %if.then6
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srli a0, a0, 48
+; RV64I-NEXT: addi a1, a0, -17
+; RV64I-NEXT: li a2, 2
+; RV64I-NEXT: bgeu a1, a2, .LBB1_4
+; RV64I-NEXT: # %bb.3: # %sw.bb8
+; RV64I-NEXT: call baz
+; RV64I-NEXT: j .LBB1_6
+; RV64I-NEXT: .LBB1_4: # %if.then6
+; RV64I-NEXT: li a1, 16
+; RV64I-NEXT: bne a0, a1, .LBB1_6
+; RV64I-NEXT: # %bb.5: # %sw.bb
+; RV64I-NEXT: call bar
+; RV64I-NEXT: .LBB1_6: # %if.end9
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: tail bat
+entry:
+ %0 = load i16, ptr %x, align 2
+ %1 = and i16 %0, -4
+ %cmp = icmp eq i16 %1, 4
+ %cmp4 = icmp sgt i16 %0, 15
+ %or.cond10 = and i1 %cmp4, %cmp
+ br i1 %or.cond10, label %if.then6, label %if.end9
+
+if.then6:
+ switch i16 %0, label %if.end9 [
+ i16 16, label %sw.bb
+ i16 17, label %sw.bb8
+ i16 18, label %sw.bb8
+ ]
+
+sw.bb:
+ tail call void @bar() #2
+ br label %if.end9
+
+sw.bb8:
+ tail call void @baz() #2
+ br label %if.end9
+
+if.end9:
+ tail call void @bat() #2
+ ret void
+}
+
+declare void @bar(...) local_unnamed_addr #1
+
+declare void @baz(...) local_unnamed_addr #1
+
+declare void @bat(...) local_unnamed_addr #1
diff --git a/llvm/test/CodeGen/RISCV/switch-width.ll b/llvm/test/CodeGen/RISCV/switch-width.ll
index d902bd3276a3ce..fa3a321d85c471 100644
--- a/llvm/test/CodeGen/RISCV/switch-width.ll
+++ b/llvm/test/CodeGen/RISCV/switch-width.ll
@@ -194,7 +194,90 @@ return:
%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
ret i32 %retval
}
+define i32 @sext_i32(i16 %a) {
+; CHECK-LABEL: sext_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a1, 16
+; CHECK-NEXT: addiw a1, a1, -1
+; CHECK-NEXT: and a2, a0, a1
+; CHECK-NEXT: beq a2, a1, .LBB5_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: slli a0, a0, 48
+; CHECK-NEXT: srai a0, a0, 48
+; CHECK-NEXT: li a1, 1
+; CHECK-NEXT: bne a0, a1, .LBB5_4
+; CHECK-NEXT: # %bb.2: # %sw.bb0
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB5_3: # %sw.bb1
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB5_4: # %sw.default
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %sext = sext i16 %a to i32
+ switch i32 %sext, label %sw.default [
+ i32 1, label %sw.bb0
+ i32 -1, label %sw.bb1
+ ]
+
+sw.bb0:
+ br label %return
+
+sw.bb1:
+ br label %return
+
+sw.default:
+ br label %return
+
+return:
+ %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
+ ret i32 %retval
+}
+
+define i32 @sext_i16(i8 %a) {
+; CHECK-LABEL: sext_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi a1, a0, 255
+; CHECK-NEXT: li a2, 255
+; CHECK-NEXT: beq a1, a2, .LBB6_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: slli a0, a0, 56
+; CHECK-NEXT: srai a0, a0, 56
+; CHECK-NEXT: slli a0, a0, 48
+; CHECK-NEXT: srli a0, a0, 48
+; CHECK-NEXT: li a1, 1
+; CHECK-NEXT: bne a0, a1, .LBB6_4
+; CHECK-NEXT: # %bb.2: # %sw.bb0
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_3: # %sw.bb1
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_4: # %sw.default
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %sext = sext i8 %a to i16
+ switch i16 %sext, label %sw.default [
+ i16 1, label %sw.bb0
+ i16 -1, label %sw.bb1
+ ]
+
+sw.bb0:
+ br label %return
+sw.bb1:
+ br label %return
+
+sw.default:
+ br label %return
+
+return:
+ %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
+ ret i32 %retval
+}
define i32 @trunc_i12(i64 %a) {
; CHECK-LABEL: trunc_i12:
@@ -202,17 +285,17 @@ define i32 @trunc_i12(i64 %a) {
; CHECK-NEXT: lui a1, 1
; CHECK-NEXT: addiw a1, a1, -1
; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: beq a0, a1, .LBB5_3
+; CHECK-NEXT: beq a0, a1, .LBB7_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 1
-; CHECK-NEXT: bne a0, a1, .LBB5_4
+; CHECK-NEXT: bne a0, a1, .LBB7_4
; CHECK-NEXT: # %bb.2: # %sw.bb0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB5_3: # %sw.bb1
+; CHECK-NEXT: .LBB7_3: # %sw.bb1
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB5_4: # %sw.default
+; CHECK-NEXT: .LBB7_4: # %sw.default
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
entry:
@@ -241,17 +324,17 @@ define i32 @trunc_i11(i64 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 2047
; CHECK-NEXT: li a1, 2047
-; CHECK-NEXT: beq a0, a1, .LBB6_3
+; CHECK-NEXT: beq a0, a1, .LBB8_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 1
-; CHECK-NEXT: bne a0, a1, .LBB6_4
+; CHECK-NEXT: bne a0, a1, .LBB8_4
; CHECK-NEXT: # %bb.2: # %sw.bb0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB6_3: # %sw.bb1
+; CHECK-NEXT: .LBB8_3: # %sw.bb1
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB6_4: # %sw.default
+; CHECK-NEXT: .LBB8_4: # %sw.default
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
entry:
@@ -281,17 +364,17 @@ define i32 @trunc_i10(i64 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 1023
; CHECK-NEXT: li a1, 1023
-; CHECK-NEXT: beq a0, a1, .LBB7_3
+; CHECK-NEXT: beq a0, a1, .LBB9_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 1
-; CHECK-NEXT: bne a0, a1, .LBB7_4
+; CHECK-NEXT: bne a0, a1, .LBB9_4
; CHECK-NEXT: # %bb.2: # %sw.bb0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB7_3: # %sw.bb1
+; CHECK-NEXT: .LBB9_3: # %sw.bb1
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB7_4: # %sw.default
+; CHECK-NEXT: .LBB9_4: # %sw.default
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
entry:
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