[llvm] [RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (PR #83375)
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 26 17:15:14 PDT 2024
https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/83375
>From 9fdf55e45046fecc5d4b368dd0506acd6656f691 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Thu, 29 Feb 2024 12:43:02 +0800
Subject: [PATCH 1/3] [RISCV] Teach RISCVMakeCompressible handle byte/half
load/store instructions for Zbc.
For targets with Zcb, this patch makes llvm generate more compress
c.lbu/lh/lhu/sb/sh instructions.
---
.../Target/RISCV/RISCVMakeCompressible.cpp | 50 +-
.../CodeGen/RISCV/make-compressible-zbc.mir | 582 ++++++++++++++++++
2 files changed, 629 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index af864ba0fbc46f..3f423450618df2 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -99,6 +99,13 @@ static unsigned log2LdstWidth(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
+ case RISCV::LBU:
+ case RISCV::SB:
+ return 0;
+ case RISCV::LH:
+ case RISCV::LHU:
+ case RISCV::SH:
+ return 1;
case RISCV::LW:
case RISCV::SW:
case RISCV::FLW:
@@ -112,17 +119,47 @@ static unsigned log2LdstWidth(unsigned Opcode) {
}
}
+// Return bit field size of immediate operand of Opcode.
+static unsigned offsetMask(unsigned Opcode) {
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected opcode");
+ case RISCV::LBU:
+ case RISCV::SB:
+ return maskTrailingOnes<unsigned>(2U);
+ case RISCV::LH:
+ case RISCV::LHU:
+ case RISCV::SH:
+ return maskTrailingOnes<unsigned>(1U);
+ case RISCV::LW:
+ case RISCV::SW:
+ case RISCV::FLW:
+ case RISCV::FSW:
+ case RISCV::LD:
+ case RISCV::SD:
+ case RISCV::FLD:
+ case RISCV::FSD:
+ return maskTrailingOnes<unsigned>(5U);
+ }
+}
+
// Return a mask for the offset bits of a non-stack-pointer based compressed
// load/store.
static uint8_t compressedLDSTOffsetMask(unsigned Opcode) {
- return 0x1f << log2LdstWidth(Opcode);
+ return offsetMask(Opcode) << log2LdstWidth(Opcode);
}
// Return true if Offset fits within a compressed stack-pointer based
// load/store.
static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) {
- return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset)
- : isShiftedUInt<6, 3>(Offset);
+ // Compressed sp-based loads and stores only work for 32/64 bits.
+ switch (log2LdstWidth(Opcode)) {
+ case 2:
+ return isShiftedUInt<6, 2>(Offset);
+ case 3:
+ return isShiftedUInt<6, 3>(Offset);
+ }
+ return false;
}
// Given an offset for a load/store, return the adjustment required to the base
@@ -147,6 +184,10 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
return false;
+ case RISCV::LBU:
+ case RISCV::LH:
+ case RISCV::LHU:
+ return STI.hasStdExtZcb();
case RISCV::LW:
case RISCV::LD:
return STI.hasStdExtCOrZca();
@@ -164,6 +205,9 @@ static bool isCompressibleStore(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
return false;
+ case RISCV::SB:
+ case RISCV::SH:
+ return STI.hasStdExtZcb();
case RISCV::SW:
case RISCV::SD:
return STI.hasStdExtCOrZca();
diff --git a/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
new file mode 100644
index 00000000000000..379c6b5ccce45f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
@@ -0,0 +1,582 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s
+# RUN: llc -o - %s -mtriple=riscv64 -mattr=+zcb -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s
+
+--- |
+ define void @store_common_value_i8(ptr %a, ptr %b, ptr %c) #0 {
+ entry:
+ store i8 0, ptr %a, align 1
+ store i8 0, ptr %b, align 1
+ store i8 0, ptr %c, align 1
+ ret void
+ }
+
+ define void @store_common_value_i16(ptr %a, ptr %b, ptr %c) #0 {
+ entry:
+ store i16 0, ptr %a, align 2
+ store i16 0, ptr %b, align 2
+ store i16 0, ptr %c, align 2
+ ret void
+ }
+
+ define void @store_common_ptr_i8(ptr %p) #0 {
+ entry:
+ store volatile i8 1, ptr %p, align 1
+ store volatile i8 3, ptr %p, align 1
+ store volatile i8 5, ptr %p, align 1
+ ret void
+ }
+
+ define void @store_common_ptr_i16(ptr %p) #0 {
+ entry:
+ store volatile i16 1, ptr %p, align 2
+ store volatile i16 3, ptr %p, align 2
+ store volatile i16 5, ptr %p, align 2
+ ret void
+ }
+
+ define void @load_common_ptr_i8(ptr %p) #0 {
+ entry:
+ %0 = load volatile i8, ptr %p, align 1
+ %a = sext i8 %0 to i32
+ %1 = load volatile i8, ptr %p, align 1
+ %2 = load volatile i8, ptr %p, align 1
+ ret void
+ }
+
+ define void @load_common_ptr_s16(ptr %p) #0 {
+ entry:
+ %0 = load volatile i16, ptr %p, align 2
+ %1 = load volatile i16, ptr %p, align 2
+ %2 = load volatile i16, ptr %p, align 2
+ ret void
+ }
+
+ define void @load_common_ptr_u16(ptr %p) #0 {
+ entry:
+ %0 = load volatile i16, ptr %p, align 2
+ %1 = load volatile i16, ptr %p, align 2
+ %2 = load volatile i16, ptr %p, align 2
+ ret void
+ }
+
+ define void @store_large_offset_i8(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i8, ptr %p, i8 100
+ store volatile i8 1, ptr %0, align 1
+ %1 = getelementptr inbounds i8, ptr %p, i8 101
+ store volatile i8 3, ptr %1, align 1
+ %2 = getelementptr inbounds i8, ptr %p, i8 102
+ store volatile i8 5, ptr %2, align 1
+ %3 = getelementptr inbounds i8, ptr %p, i8 103
+ store volatile i8 7, ptr %3, align 1
+ ret void
+ }
+
+ define void @store_large_offset_i16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ store volatile i16 1, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 100
+ store volatile i16 3, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 101
+ store volatile i16 3, ptr %1, align 2
+ %3 = getelementptr inbounds i16, ptr %p, i16 101
+ store volatile i16 7, ptr %3, align 2
+ ret void
+ }
+
+ define void @load_large_offset_i8(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i8, ptr %p, i8 100
+ %a = load volatile i8, ptr %0
+ %1 = getelementptr inbounds i8, ptr %p, i8 101
+ %b = load volatile i8, ptr %1
+ %2 = getelementptr inbounds i8, ptr %p, i8 102
+ %c = load volatile i8, ptr %2
+ %3 = getelementptr inbounds i8, ptr %p, i8 103
+ %d = load volatile i8, ptr %3
+ ret void
+ }
+
+ define void @load_large_offset_s16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ %a = load volatile i16, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 100
+ %b = load volatile i16, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 101
+ %c = load volatile i16, ptr %2, align 2
+ %3 = getelementptr inbounds i16, ptr %p, i16 101
+ %d = load volatile i16, ptr %3, align 2
+ ret void
+ }
+
+ define void @load_large_offset_u16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ %a = load volatile i16, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 100
+ %b = load volatile i16, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 101
+ %c = load volatile i16, ptr %2, align 2
+ %3 = getelementptr inbounds i16, ptr %p, i16 101
+ %d = load volatile i16, ptr %3, align 2
+ ret void
+ }
+ define void @store_large_offset_no_opt_i8(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i8, ptr %p, i8 100
+ store volatile i8 1, ptr %0, align 1
+ %1 = getelementptr inbounds i8, ptr %p, i8 101
+ store volatile i8 3, ptr %1, align 1
+ %2 = getelementptr inbounds i8, ptr %p, i8 104
+ store volatile i8 5, ptr %2, align 1
+ ret void
+ }
+
+ define void @store_large_offset_no_opt_i16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ %a = load volatile i16, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 100
+ %b = load volatile i16, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 101
+ %c = load volatile i16, ptr %2, align 2
+ %3 = getelementptr inbounds i16, ptr %p, i16 102
+ %d = load volatile i16, ptr %3, align 2
+ ret void
+ }
+
+ define void @load_large_offset_no_opt_i8(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i8, ptr %p, i8 100
+ %a = load volatile i8, ptr %0
+ %1 = getelementptr inbounds i8, ptr %p, i8 101
+ %b = load volatile i8, ptr %1
+ %2 = getelementptr inbounds i8, ptr %p, i8 103
+ %c = load volatile i8, ptr %2
+ ret void
+ }
+
+ define void @load_large_offset_no_opt_s16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ %a = load volatile i16, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 101
+ %c = load volatile i16, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 102
+ %d = load volatile i16, ptr %2, align 2
+ ret void
+ }
+
+ define void @load_large_offset_no_opt_u16(ptr %p) #0 {
+ entry:
+ %0 = getelementptr inbounds i16, ptr %p, i16 100
+ %a = load volatile i16, ptr %0, align 2
+ %1 = getelementptr inbounds i16, ptr %p, i16 101
+ %c = load volatile i16, ptr %1, align 2
+ %2 = getelementptr inbounds i16, ptr %p, i16 102
+ %d = load volatile i16, ptr %2, align 2
+ ret void
+ }
+ attributes #0 = { minsize }
+
+...
+---
+name: store_common_value_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; CHECK-LABEL: name: store_common_value_i8
+ ; CHECK: liveins: $x10, $x11, $x12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x13 = ADDI $x0, 0
+ ; CHECK-NEXT: SB $x13, killed renamable $x10, 0 :: (store (s8) into %ir.a)
+ ; CHECK-NEXT: SB $x13, killed renamable $x11, 0 :: (store (s8) into %ir.b)
+ ; CHECK-NEXT: SB $x13, killed renamable $x12, 0 :: (store (s8) into %ir.c)
+ ; CHECK-NEXT: PseudoRET
+ SB $x0, killed renamable $x10, 0 :: (store (s8) into %ir.a)
+ SB $x0, killed renamable $x11, 0 :: (store (s8) into %ir.b)
+ SB $x0, killed renamable $x12, 0 :: (store (s8) into %ir.c)
+ PseudoRET
+
+...
+---
+name: store_common_value_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12
+
+ ; CHECK-LABEL: name: store_common_value_i16
+ ; CHECK: liveins: $x10, $x11, $x12
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x13 = ADDI $x0, 0
+ ; CHECK-NEXT: SH $x13, killed renamable $x10, 0 :: (store (s16) into %ir.a)
+ ; CHECK-NEXT: SH $x13, killed renamable $x11, 0 :: (store (s16) into %ir.b)
+ ; CHECK-NEXT: SH $x13, killed renamable $x12, 0 :: (store (s16) into %ir.c)
+ ; CHECK-NEXT: PseudoRET
+ SH $x0, killed renamable $x10, 0 :: (store (s16) into %ir.a)
+ SH $x0, killed renamable $x11, 0 :: (store (s16) into %ir.b)
+ SH $x0, killed renamable $x12, 0 :: (store (s16) into %ir.c)
+ PseudoRET
+
+...
+---
+name: store_common_ptr_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: store_common_ptr_i8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x11 = ADDI $x0, 3
+ SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x11 = ADDI $x0, 5
+ SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ PseudoRET
+
+...
+---
+name: store_common_ptr_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: store_common_ptr_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x11 = ADDI $x0, 3
+ SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x11 = ADDI $x0, 5
+ SH killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_i8
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_common_ptr_i8
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_s16
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_common_ptr_s16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LH killed $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LH renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ dead $x10 = LH renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ dead $x10 = LH killed renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_u16
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_common_ptr_u16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LHU killed $x11, 0 :: (volatile load (s16) from %ir.p)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LHU renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ dead $x10 = LHU renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ dead $x10 = LHU killed renamable $x16, 0 :: (volatile load (s16) from %ir.p)
+ PseudoRET
+
+...
+---
+name: store_large_offset_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: store_large_offset_i8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: $x12 = ADDI $x10, 100
+ ; CHECK-NEXT: SB killed renamable $x11, $x12, 0 :: (volatile store (s8) into %ir.0)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x11, $x12, 1 :: (volatile store (s8) into %ir.1)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x11, $x12, 2 :: (volatile store (s8) into %ir.2)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: SB killed renamable $x11, killed $x12, 3 :: (volatile store (s8) into %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SB killed renamable $x11, renamable $x10, 100 :: (volatile store (s8) into %ir.0)
+ renamable $x11 = ADDI $x0, 3
+ SB killed renamable $x11, renamable $x10, 101 :: (volatile store (s8) into %ir.1)
+ renamable $x11 = ADDI $x0, 5
+ SB killed renamable $x11, renamable $x10, 102 :: (volatile store (s8) into %ir.2)
+ renamable $x11 = ADDI $x0, 7
+ SB killed renamable $x11, killed renamable $x10, 103 :: (volatile store (s8) into %ir.3)
+ PseudoRET
+
+...
+---
+name: store_large_offset_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+ ; CHECK-LABEL: name: store_large_offset_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: $x12 = ADDI $x10, 200
+ ; CHECK-NEXT: SH killed renamable $x11, $x12, 0 :: (volatile store (s16) into %ir.0)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x11, $x12, 0 :: (volatile store (s16) into %ir.1)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x11, $x12, 2 :: (volatile store (s16) into %ir.2)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 7
+ ; CHECK-NEXT: SH killed renamable $x11, killed $x12, 2 :: (volatile store (s16) into %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SH killed renamable $x11, renamable $x10, 200 :: (volatile store (s16) into %ir.0)
+ renamable $x11 = ADDI $x0, 3
+ SH killed renamable $x11, renamable $x10, 200 :: (volatile store (s16) into %ir.1)
+ renamable $x11 = ADDI $x0, 5
+ SH killed renamable $x11, renamable $x10, 202 :: (volatile store (s16) into %ir.2)
+ renamable $x11 = ADDI $x0, 7
+ SH killed renamable $x11, killed renamable $x10, 202 :: (volatile store (s16) into %ir.3)
+ PseudoRET
+
+...
+---
+name: load_large_offset_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_i8
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 100
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 0 :: (volatile load (s8) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 1 :: (volatile load (s8) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 2 :: (volatile load (s8) from %ir.2)
+ ; CHECK-NEXT: dead $x10 = LBU killed $x11, 3 :: (volatile load (s8) from %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LBU renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ dead $x10 = LBU renamable $x16, 101 :: (volatile load (s8) from %ir.1)
+ dead $x10 = LBU renamable $x16, 102 :: (volatile load (s8) from %ir.2)
+ dead $x10 = LBU killed renamable $x16, 103 :: (volatile load (s8) from %ir.3)
+ PseudoRET
+
+...
+---
+name: load_large_offset_s16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_s16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 100
+ ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LH $x11, 0 :: (volatile load (s16) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LH $x11, 2 :: (volatile load (s16) from %ir.2)
+ ; CHECK-NEXT: dead $x10 = LH killed $x11, 2 :: (volatile load (s16) from %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LH renamable $x16, 100 :: (volatile load (s16) from %ir.0)
+ dead $x10 = LH renamable $x16, 100 :: (volatile load (s16) from %ir.1)
+ dead $x10 = LH renamable $x16, 102 :: (volatile load (s16) from %ir.2)
+ dead $x10 = LH killed renamable $x16, 102 :: (volatile load (s16) from %ir.3)
+ PseudoRET
+
+...
+---
+name: load_large_offset_u16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_u16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x11 = ADDI $x16, 100
+ ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LHU $x11, 0 :: (volatile load (s16) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LHU $x11, 2 :: (volatile load (s16) from %ir.2)
+ ; CHECK-NEXT: dead $x10 = LHU killed $x11, 2 :: (volatile load (s16) from %ir.3)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LHU renamable $x16, 100 :: (volatile load (s16) from %ir.0)
+ dead $x10 = LHU renamable $x16, 100 :: (volatile load (s16) from %ir.1)
+ dead $x10 = LHU renamable $x16, 102 :: (volatile load (s16) from %ir.2)
+ dead $x10 = LHU killed renamable $x16, 102 :: (volatile load (s16) from %ir.3)
+ PseudoRET
+
+...
+---
+name: store_large_offset_no_opt_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: store_large_offset_no_opt_i8
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x16, 100 :: (volatile store (s8) into %ir.0)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x16, 101 :: (volatile store (s8) into %ir.1)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x11, renamable $x16, 104 :: (volatile store (s8) into %ir.2)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SB killed renamable $x11, renamable $x16, 100 :: (volatile store (s8) into %ir.0)
+ renamable $x11 = ADDI $x0, 3
+ SB killed renamable $x11, renamable $x16, 101 :: (volatile store (s8) into %ir.1)
+ renamable $x11 = ADDI $x0, 5
+ SB killed renamable $x11, renamable $x16, 104 :: (volatile store (s8) into %ir.2)
+ PseudoRET
+
+...
+---
+name: store_large_offset_no_opt_i16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: store_large_offset_no_opt_i16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x16, 200 :: (volatile store (s16) into %ir.0)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x16, 202 :: (volatile store (s16) into %ir.1)
+ ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x11, renamable $x16, 204 :: (volatile store (s16) into %ir.2)
+ ; CHECK-NEXT: PseudoRET
+ renamable $x11 = ADDI $x0, 1
+ SH killed renamable $x11, renamable $x16, 200 :: (volatile store (s16) into %ir.0)
+ renamable $x11 = ADDI $x0, 3
+ SH killed renamable $x11, renamable $x16, 202 :: (volatile store (s16) into %ir.1)
+ renamable $x11 = ADDI $x0, 5
+ SH killed renamable $x11, renamable $x16, 204 :: (volatile store (s16) into %ir.2)
+ PseudoRET
+
+...
+---
+name: load_large_offset_no_opt_i8
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_no_opt_i8
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead $x10 = LBU renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LBU renamable $x16, 101 :: (volatile load (s8) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LBU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LBU renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ dead $x10 = LBU renamable $x16, 101 :: (volatile load (s8) from %ir.1)
+ dead $x10 = LBU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2)
+ PseudoRET
+
+...
+---
+name: load_large_offset_no_opt_s16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_no_opt_s16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead $x10 = LH renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LH renamable $x16, 102 :: (volatile load (s8) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LH killed renamable $x16, 104 :: (volatile load (s8) from %ir.2)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LH renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ dead $x10 = LH renamable $x16, 102 :: (volatile load (s8) from %ir.1)
+ dead $x10 = LH killed renamable $x16, 104 :: (volatile load (s8) from %ir.2)
+ PseudoRET
+
+...
+---
+name: load_large_offset_no_opt_u16
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; CHECK-LABEL: name: load_large_offset_no_opt_u16
+ ; CHECK: liveins: $x16
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead $x10 = LHU renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ ; CHECK-NEXT: dead $x10 = LHU renamable $x16, 102 :: (volatile load (s8) from %ir.1)
+ ; CHECK-NEXT: dead $x10 = LHU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2)
+ ; CHECK-NEXT: PseudoRET
+ dead $x10 = LHU renamable $x16, 100 :: (volatile load (s8) from %ir.0)
+ dead $x10 = LHU renamable $x16, 102 :: (volatile load (s8) from %ir.1)
+ dead $x10 = LHU killed renamable $x16, 104 :: (volatile load (s8) from %ir.2)
+ PseudoRET
+
+...
>From efb6a7ea51d3e557d84ac400e5afa050fc3d9fd3 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Tue, 26 Mar 2024 14:39:04 +0800
Subject: [PATCH 2/3] Update test cases.
---
.../CodeGen/RISCV/make-compressible-zbc.mir | 59 ++++++++++---------
1 file changed, 30 insertions(+), 29 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
index 379c6b5ccce45f..87ec0cc4731e40 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
@@ -237,19 +237,19 @@ body: |
; CHECK-LABEL: name: store_common_ptr_i8
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
- ; CHECK-NEXT: SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
- ; CHECK-NEXT: SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
- ; CHECK-NEXT: SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x16 = ADDI $x0, 1
+ ; CHECK-NEXT: SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x16 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x16 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
; CHECK-NEXT: PseudoRET
- renamable $x11 = ADDI $x0, 1
- SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- renamable $x11 = ADDI $x0, 3
- SB killed renamable $x11, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- renamable $x11 = ADDI $x0, 5
- SB killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x16 = ADDI $x0, 1
+ SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x16 = ADDI $x0, 3
+ SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x16 = ADDI $x0, 5
+ SB killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
PseudoRET
...
@@ -263,19 +263,19 @@ body: |
; CHECK-LABEL: name: store_common_ptr_i16
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
- ; CHECK-NEXT: SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- ; CHECK-NEXT: renamable $x11 = ADDI $x0, 3
- ; CHECK-NEXT: SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- ; CHECK-NEXT: renamable $x11 = ADDI $x0, 5
- ; CHECK-NEXT: SH killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x16 = ADDI $x0, 1
+ ; CHECK-NEXT: SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x16 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x16 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
; CHECK-NEXT: PseudoRET
- renamable $x11 = ADDI $x0, 1
- SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- renamable $x11 = ADDI $x0, 3
- SH killed renamable $x11, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- renamable $x11 = ADDI $x0, 5
- SH killed renamable $x11, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x16 = ADDI $x0, 1
+ SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x16 = ADDI $x0, 3
+ SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x16 = ADDI $x0, 5
+ SH killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
PseudoRET
...
@@ -288,12 +288,13 @@ body: |
; CHECK-LABEL: name: load_common_ptr_i8
; CHECK: liveins: $x16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
- ; CHECK-NEXT: dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
- ; CHECK-NEXT: dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LBU $x11, 0 :: (volatile load (s8) from %ir.p)
+ ; CHECK-NEXT: dead $x10 = LBU killed $x11, 0 :: (volatile load (s8) from %ir.p)
; CHECK-NEXT: PseudoRET
- dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
- dead $x10 = LB renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ dead $x10 = LBU renamable $x16, 0 :: (volatile load (s8) from %ir.p)
+ dead $x10 = LBU renamable $x16, 0 :: (volatile load (s8) from %ir.p)
dead $x10 = LBU killed renamable $x16, 0 :: (volatile load (s8) from %ir.p)
PseudoRET
>From c8009e6511e3eb67e6d2637f21c042c59deb1d24 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Wed, 27 Mar 2024 08:12:20 +0800
Subject: [PATCH 3/3] Another testcase fix.
---
.../CodeGen/RISCV/make-compressible-zbc.mir | 58 ++++++++++---------
1 file changed, 30 insertions(+), 28 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
index 87ec0cc4731e40..89a6ca7af9be13 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible-zbc.mir
@@ -232,24 +232,25 @@ name: store_common_ptr_i8
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $x10
+ liveins: $x16
; CHECK-LABEL: name: store_common_ptr_i8
- ; CHECK: liveins: $x10
+ ; CHECK: liveins: $x16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x16 = ADDI $x0, 1
- ; CHECK-NEXT: SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- ; CHECK-NEXT: renamable $x16 = ADDI $x0, 3
- ; CHECK-NEXT: SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- ; CHECK-NEXT: renamable $x16 = ADDI $x0, 5
- ; CHECK-NEXT: SB killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: SB killed renamable $x10, $x11, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 3
+ ; CHECK-NEXT: SB killed renamable $x10, $x11, 0 :: (volatile store (s8) into %ir.p)
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 5
+ ; CHECK-NEXT: SB killed renamable $x10, killed $x11, 0 :: (volatile store (s8) into %ir.p)
; CHECK-NEXT: PseudoRET
- renamable $x16 = ADDI $x0, 1
- SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- renamable $x16 = ADDI $x0, 3
- SB killed renamable $x16, renamable $x10, 0 :: (volatile store (s8) into %ir.p)
- renamable $x16 = ADDI $x0, 5
- SB killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x10 = ADDI $x0, 1
+ SB killed renamable $x10, renamable $x16, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x10 = ADDI $x0, 3
+ SB killed renamable $x10, renamable $x16, 0 :: (volatile store (s8) into %ir.p)
+ renamable $x10 = ADDI $x0, 5
+ SB killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s8) into %ir.p)
PseudoRET
...
@@ -258,24 +259,25 @@ name: store_common_ptr_i16
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: $x10
+ liveins: $x16
; CHECK-LABEL: name: store_common_ptr_i16
- ; CHECK: liveins: $x10
+ ; CHECK: liveins: $x16
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $x16 = ADDI $x0, 1
- ; CHECK-NEXT: SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- ; CHECK-NEXT: renamable $x16 = ADDI $x0, 3
- ; CHECK-NEXT: SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- ; CHECK-NEXT: renamable $x16 = ADDI $x0, 5
- ; CHECK-NEXT: SH killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 1
+ ; CHECK-NEXT: $x11 = ADDI $x16, 0
+ ; CHECK-NEXT: SH killed renamable $x10, $x11, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 3
+ ; CHECK-NEXT: SH killed renamable $x10, $x11, 0 :: (volatile store (s16) into %ir.p)
+ ; CHECK-NEXT: renamable $x10 = ADDI $x0, 5
+ ; CHECK-NEXT: SH killed renamable $x10, killed $x11, 0 :: (volatile store (s16) into %ir.p)
; CHECK-NEXT: PseudoRET
- renamable $x16 = ADDI $x0, 1
- SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- renamable $x16 = ADDI $x0, 3
- SH killed renamable $x16, renamable $x10, 0 :: (volatile store (s16) into %ir.p)
- renamable $x16 = ADDI $x0, 5
- SH killed renamable $x16, killed renamable $x10, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x10 = ADDI $x0, 1
+ SH killed renamable $x10, renamable $x16, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x10 = ADDI $x0, 3
+ SH killed renamable $x10, renamable $x16, 0 :: (volatile store (s16) into %ir.p)
+ renamable $x10 = ADDI $x0, 5
+ SH killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s16) into %ir.p)
PseudoRET
...
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