[llvm] goldsteinn/x86 nneg uitofp (PR #86694)
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Tue Mar 26 10:01:11 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: None (goldsteinn)
<details>
<summary>Changes</summary>
- **[X86] Add tests for `uitofp nneg` -> `sitofp`; NFC**
- **[X86] Use `nneg` flag when trying to convert `uitofp` -> `sitofp`**
---
Full diff: https://github.com/llvm/llvm-project/pull/86694.diff
2 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+3-2)
- (modified) llvm/test/CodeGen/X86/uint_to_fp.ll (+54)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1ce742a7c19a74..c5b391df20c837 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48270,7 +48270,7 @@ static SDValue combineAndShuffleNot(SDNode *N, SelectionDAG &DAG,
// We do not split for SSE at all, but we need to split vectors for AVX1 and
// AVX2.
- if (!Subtarget.useAVX512Regs() && VT.is512BitVector() &&
+ if (!Subtarget.useAVX512Regs() && VT.is512BitVector() &&
TLI.isTypeLegal(VT.getHalfNumVectorElementsVT(*DAG.getContext()))) {
SDValue LoX, HiX;
std::tie(LoX, HiX) = splitVector(X, DAG, DL);
@@ -54065,7 +54065,8 @@ static SDValue combineUIntToFP(SDNode *N, SelectionDAG &DAG,
// Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
// optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
// the optimization here.
- if (DAG.SignBitIsZero(Op0)) {
+ SDNodeFlags Flags = N->getFlags();
+ if (Flags.hasNonNeg() || DAG.SignBitIsZero(Op0)) {
if (IsStrict)
return DAG.getNode(ISD::STRICT_SINT_TO_FP, SDLoc(N), {VT, MVT::Other},
{N->getOperand(0), Op0});
diff --git a/llvm/test/CodeGen/X86/uint_to_fp.ll b/llvm/test/CodeGen/X86/uint_to_fp.ll
index d8e0b61ed199fa..8c8cbb151974d6 100644
--- a/llvm/test/CodeGen/X86/uint_to_fp.ll
+++ b/llvm/test/CodeGen/X86/uint_to_fp.ll
@@ -25,3 +25,57 @@ entry:
store float %1, ptr %y
ret void
}
+
+define float @test_without_nneg(i32 %x) nounwind {
+; X86-LABEL: test_without_nneg:
+; X86: ## %bb.0:
+; X86-NEXT: pushl %eax
+; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: cvtsd2ss %xmm0, %xmm0
+; X86-NEXT: movss %xmm0, (%esp)
+; X86-NEXT: flds (%esp)
+; X86-NEXT: popl %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: test_without_nneg:
+; X64: ## %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: cvtsi2ss %rax, %xmm0
+; X64-NEXT: retq
+ %r = uitofp i32 %x to float
+ ret float %r
+}
+
+define float @test_with_nneg(i32 %x) nounwind {
+; X86-LABEL: test_with_nneg:
+; X86: ## %bb.0:
+; X86-NEXT: pushl %eax
+; X86-NEXT: cvtsi2ssl {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: movss %xmm0, (%esp)
+; X86-NEXT: flds (%esp)
+; X86-NEXT: popl %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: test_with_nneg:
+; X64: ## %bb.0:
+; X64-NEXT: cvtsi2ss %edi, %xmm0
+; X64-NEXT: retq
+ %r = uitofp nneg i32 %x to float
+ ret float %r
+}
+
+define <4 x float> @test_with_nneg_vec(<4 x i32> %x) nounwind {
+; X86-LABEL: test_with_nneg_vec:
+; X86: ## %bb.0:
+; X86-NEXT: cvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_with_nneg_vec:
+; X64: ## %bb.0:
+; X64-NEXT: cvtdq2ps %xmm0, %xmm0
+; X64-NEXT: retq
+ %r = uitofp nneg <4 x i32> %x to <4 x float>
+ ret <4 x float> %r
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/86694
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