[llvm] [RISCV] Add scheduling information for SiFive VCIX (PR #86093)

[Michael Maitland via llvm-commits]

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@@ -307,44 +307,44 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
     let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
-      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>;
-      def "PseudoVC_V_" # NAME # "_SE_" # m.MX : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>;
+      def "PseudoVC_" # NAME # "_SE_" # m.MX : VPseudoVC_X<OpClass, RS1Class>, Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
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michaelmaitland wrote:

That makes sense. I have one nitty comment for these: can you change to have no more than 80 characters per line?


https://github.com/llvm/llvm-project/pull/86093