[llvm] [BOLT][AArch64] Fixes assertion errors occurred when perf2bolt was executed (PR #83394)

[Ádám Kallai via llvm-commits]

kaadam wrote:

Hi @yota9, Sorry for the delayed response.
Started to work on to handle these two patterns maybe you can give me some pointers about them.  
Preprocessing indirect branch we should extract PCRelBase, and JumpTable (label address) + Offset if it is possible.

Considering this pattern, this adr  instruction its address could be PCRelbase, as I tried to follow the original logic maybe it could be "JT" as well. But we only have the address of the entry in sigall_set "section", should we know about the label address of the sigall_set?

```
      //   adr     x6, 0x219fb0 <sigall_set+0x88> => PCRelBase, JT?
      //   add     x6, x6, x14, lsl #2
      //   ldr     w7, [x6]
      //   add     x6, x6, w7, sxtw
      //   br      x6
```
a snippet of the print-cfg:

```
.Ltmp7286 (10 instructions, align : 1)
  CFI State : 0
  Predecessors: .LFT5416
    00000268:   ldp     q5, q6, [x1], #0x20
    0000026c:   stp     q1, q2, [x3], #0x20
    00000270:   and     x3, x3, #0xfffffffffffffff0
    00000274:   sub     x2, x2, #0x20
    00000278:   hint    #0x0 # NOP: 1
    0000027c:   adr     x6, #-365276
    00000280:   add     x6, x6, x14, lsl #2
    00000284:   ldr     w7, [x6]
    00000288:   add     x6, x6, w7, sxtw
    0000028c:   br      x6 # UNKNOWN CONTROL FLOW
  CFI State: 0
```

Binary attached: 
[bubblesort_arm64_static.zip](https://github.com/llvm/llvm-project/files/14758180/bubblesort_arm64_static.zip)


https://github.com/llvm/llvm-project/pull/83394