[llvm] [TableGen][SchedMachineModel] Improve way to create WriteLatencyTable. (PR #86654)

[via llvm-commits]

https://github.com/lcvon007 created https://github.com/llvm/llvm-project/pull/86654

Tablegen will generate xxxWriteLatencyTable to record the
latency information for schedule class in xxxGenSubtargetInfo.inc,
and element in latency table is {Cycles, WriteResourceID}, each
target may have multiple processors using different SchedModels,
and WriteResourceId will not zero if any of SchedModel define
ReadAdvance that its ValidWrites includes SchedWrite
(as the old hasReadOfWrite function does).

Use the new method(Only use currect ProcModel) to check if we
hasReadWrite doesn't affect the usage of LatencyTable, and it
has two good points:
1. It doesn't need traverse all the ProcModels
2. It may generate simpler latency table with less elements.


>From c4f2ab1ef583ea3ef816bc6dbd0a009825f6a99c Mon Sep 17 00:00:00 2001
From: laichunfeng <laichunfeng at tencent.com>
Date: Tue, 26 Mar 2024 18:21:32 +0800
Subject: [PATCH] [TableGen][SchedMachineModel] Improve way to create
 WriteLatencyTable.

Tablegen will generate xxxWriteLatencyTable to record the
latency information for schedule class in xxxGenSubtargetInfo.inc,
and element in latency table is {Cycles, WriteResourceID}, each
target may have multiple processors using different SchedModels,
and WriteResourceId will not zero if any of SchedModel define
ReadAdvance that its ValidWrites includes SchedWrite
(as the old hasReadOfWrite function does).

Use the new method(Only use currect ProcModel) to check if we
hasReadWrite doesn't affect the usage of LatencyTable, and it
has two good points:
1. It doesn't need traverse all the ProcModels
2. It may generate simpler latency table with less elements.
---
 llvm/utils/TableGen/Common/CodeGenSchedule.cpp | 15 +++++++--------
 llvm/utils/TableGen/Common/CodeGenSchedule.h   |  3 ++-
 llvm/utils/TableGen/SubtargetEmitter.cpp       |  4 ++--
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 0e81623a6aa388..a4192a44c766af 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -746,14 +746,13 @@ unsigned CodeGenSchedModels::getSchedRWIdx(const Record *Def,
   return I == RWVec.end() ? 0 : std::distance(RWVec.begin(), I);
 }
 
-bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
-  for (auto &ProcModel : ProcModels) {
-    const RecVec &RADefs = ProcModel.ReadAdvanceDefs;
-    for (auto &RADef : RADefs) {
-      RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
-      if (is_contained(ValidWrites, WriteDef))
-        return true;
-    }
+bool CodeGenSchedModels::hasReadOfWrite(
+    const Record *WriteDef, const CodeGenProcModel &ProcModel) const {
+  const RecVec &RADefs = ProcModel.ReadAdvanceDefs;
+  for (auto &RADef : RADefs) {
+    RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
+    if (is_contained(ValidWrites, WriteDef))
+      return true;
   }
   return false;
 }
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h
index 61980e7e196e5d..e6e954d3b167fc 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -537,7 +537,8 @@ class CodeGenSchedModels {
   unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
 
   // Return true if the given write record is referenced by a ReadAdvance.
-  bool hasReadOfWrite(Record *WriteDef) const;
+  bool hasReadOfWrite(const Record *WriteDef,
+                      const CodeGenProcModel &ProcModel) const;
 
   // Get a SchedClass from its index.
   CodeGenSchedClass &getSchedClass(unsigned Idx) {
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 2e2c57b802ee54..edcfb0fa6f0378 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1122,8 +1122,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
       WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
       // If this Write is not referenced by a ReadAdvance, don't distinguish it
       // from other WriteLatency entries.
-      if (!SchedModels.hasReadOfWrite(
-              SchedModels.getSchedWrite(WriteID).TheDef)) {
+      if (!SchedModels.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef,
+                                      ProcModel)) {
         WriteID = 0;
       }
       WLEntry.WriteResourceID = WriteID;