[llvm] Fix https://github.com/llvm/llvm-project/issues/75998 (PR #82661)

[Eleanor Bonnici via llvm-commits]

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@@ -369,7 +369,8 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {
 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
   let AltOrders = [(and tcGPR, tGPR)];
   let AltOrderSelect = [{
-      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
+      return MF.getSubtarget<ARMSubtarget>().isThumb1Only() ||
+        MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true);
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eleanor-arm wrote:

They are a bit similar but not the same. The optimization filter in ARMTargetLowering::IsEligibleForTailCallOptimization also checks the number of arguments to decide whether it's possible to optimize, which is the most relevant factor for that purpose. Here we just encode which registers to use if the optimization is already happening.

https://github.com/llvm/llvm-project/pull/82661