[llvm] [X86] Support Immediate Folding for CCMP/CTEST. (PR #86616)
Freddy Ye via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 19:04:37 PDT 2024
https://github.com/FreddyLeaf created https://github.com/llvm/llvm-project/pull/86616
- pre-commit test
- [X86] Support Immediate Folding for CCMP/CTEST.
>From 709097e8bdefd2d814d872af069c70c72a87ceb8 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 26 Mar 2024 09:54:56 +0800
Subject: [PATCH 1/2] pre-commit test
---
llvm/test/CodeGen/X86/apx/foldimmediate.mir | 143 ++++++++++++++++++++
1 file changed, 143 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/apx/foldimmediate.mir
diff --git a/llvm/test/CodeGen/X86/apx/foldimmediate.mir b/llvm/test/CodeGen/X86/apx/foldimmediate.mir
new file mode 100644
index 00000000000000..5fd5ae9c1ca9f1
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/foldimmediate.mir
@@ -0,0 +1,143 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=x86_64-- -run-pass=peephole-opt %s -o - | FileCheck %s
+--- |
+ define void @foldImmediate() { ret void }
+...
+---
+# Check that immediates can be folded into ALU instructions.
+name: foldImmediate
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr32 }
+ - { id: 2, class: gr32 }
+ - { id: 3, class: gr32 }
+ - { id: 4, class: gr32 }
+ - { id: 5, class: gr32 }
+ - { id: 6, class: gr32 }
+ - { id: 7, class: gr64 }
+ - { id: 8, class: gr64 }
+ - { id: 9, class: gr64 }
+ - { id: 10, class: gr64 }
+ - { id: 11, class: gr64 }
+ - { id: 12, class: gr64 }
+ - { id: 13, class: gr64 }
+ - { id: 14, class: gr64 }
+ - { id: 15, class: gr64 }
+ - { id: 16, class: gr32 }
+ - { id: 17, class: gr64 }
+ - { id: 18, class: gr32 }
+
+body: |
+ bb.0:
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: foldImmediate
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 81
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[ADD32ri:%[0-9]+]]:gr32 = ADD32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[ADD32ri]]
+ ; CHECK-NEXT: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[SUB32ri]]
+ ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[AND32ri]]
+ ; CHECK-NEXT: [[OR32ri:%[0-9]+]]:gr32 = OR32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[OR32ri]]
+ ; CHECK-NEXT: [[XOR32ri:%[0-9]+]]:gr32 = XOR32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[XOR32ri]]
+ ; CHECK-NEXT: TEST32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit $eflags
+ ; CHECK-NEXT: CMP32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit $eflags
+ ; CHECK-NEXT: [[ADC32ri:%[0-9]+]]:gr32 = ADC32ri [[COPY]], 81, implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: NOOP implicit [[ADC32ri]]
+ ; CHECK-NEXT: [[SBB32ri:%[0-9]+]]:gr32 = SBB32ri [[COPY]], 81, implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: NOOP implicit [[SBB32ri]]
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32ri]], %subreg.sub_32bit
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[ADD64ri32_:%[0-9]+]]:gr64 = ADD64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[ADD64ri32_]]
+ ; CHECK-NEXT: [[SUB64ri32_:%[0-9]+]]:gr64 = SUB64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[SUB64ri32_]]
+ ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[AND64ri32_]]
+ ; CHECK-NEXT: [[OR64ri32_:%[0-9]+]]:gr64 = OR64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[OR64ri32_]]
+ ; CHECK-NEXT: [[XOR64ri32_:%[0-9]+]]:gr64 = XOR64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit [[XOR64ri32_]]
+ ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64 = MOV32ri64 81
+ ; CHECK-NEXT: NOOP implicit [[MOV32ri64_]]
+ ; CHECK-NEXT: TEST64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit $eflags
+ ; CHECK-NEXT: [[ADC64ri32_:%[0-9]+]]:gr64 = ADC64ri32 [[COPY1]], 81, implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: NOOP implicit [[ADC64ri32_]]
+ ; CHECK-NEXT: [[SBB64ri32_:%[0-9]+]]:gr64 = SBB64ri32 [[COPY1]], 81, implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: NOOP implicit [[SBB64ri32_]]
+ ; CHECK-NEXT: CMP64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit $eflags
+ ; CHECK-NEXT: CMP64rr [[SUBREG_TO_REG]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: NOOP implicit $eflags
+ %0 = MOV32ri 81
+ %1 = COPY $edi
+ %2 = ADD32rr %0, %1, implicit-def $eflags
+ NOOP implicit %2
+
+ %3 = SUB32rr %1, %0, implicit-def $eflags
+ NOOP implicit %3
+
+ %4 = AND32rr %0, %1, implicit-def $eflags
+ NOOP implicit %4
+
+ %5 = OR32rr %0, %1, implicit-def $eflags
+ NOOP implicit %5
+
+ %6 = XOR32rr %0, %1, implicit-def $eflags
+ NOOP implicit %6
+
+ TEST32rr %0, %1, implicit-def $eflags
+ NOOP implicit $eflags
+
+ CMP32rr %1, %0, implicit-def $eflags
+ NOOP implicit $eflags
+
+ %16 = ADC32rr %0, %1, implicit-def $eflags, implicit $eflags
+ NOOP implicit %16
+
+ %18 = SBB32rr %1, %0, implicit-def $eflags, implicit $eflags
+ NOOP implicit %18
+
+ %7 = SUBREG_TO_REG 0, killed %0:gr32, %subreg.sub_32bit
+ %8 = COPY $rsi
+ %9 = ADD64rr %7, %8, implicit-def $eflags
+ NOOP implicit %9
+
+ %10 = SUB64rr %8, %7, implicit-def $eflags
+ NOOP implicit %10
+
+ %11 = AND64rr %8, %7, implicit-def $eflags
+ NOOP implicit %11
+
+ %12 = OR64rr %8, %7, implicit-def $eflags
+ NOOP implicit %12
+
+ %13 = XOR64rr %8, %7, implicit-def $eflags
+ NOOP implicit %13
+
+ %14 = COPY %7
+ NOOP implicit %14
+
+ TEST64rr %8, %7, implicit-def $eflags
+ NOOP implicit $eflags
+
+ %15 = ADC64rr %8, %7, implicit-def $eflags, implicit $eflags
+ NOOP implicit %15
+
+ %17 = SBB64rr %8, %7, implicit-def $eflags, implicit $eflags
+ NOOP implicit %17
+
+ CMP64rr %8, %7, implicit-def $eflags
+ NOOP implicit $eflags
+ CMP64rr %7, %8, implicit-def $eflags
+ NOOP implicit $eflags
+...
>From 19168512547a5577077a88b66dd03d92a5b28dc7 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 26 Mar 2024 09:55:55 +0800
Subject: [PATCH 2/2] [X86] Support Immediate Folding for CCMP/CTEST.
---
llvm/lib/Target/X86/X86InstrInfo.cpp | 4 ++++
llvm/test/CodeGen/X86/apx/foldimmediate.mir | 20 ++++++++++----------
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index eb42a4b2119d5e..65255c78225a7b 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5595,9 +5595,13 @@ static unsigned convertALUrr2ALUri(unsigned Opc) {
case X86::FROM: \
return X86::TO;
FROM_TO(TEST64rr, TEST64ri32)
+ FROM_TO(CTEST64rr, CTEST64ri32)
FROM_TO(CMP64rr, CMP64ri32)
+ FROM_TO(CCMP64rr, CCMP64ri32)
FROM_TO(TEST32rr, TEST32ri)
+ FROM_TO(CTEST32rr, CTEST32ri)
FROM_TO(CMP32rr, CMP32ri)
+ FROM_TO(CCMP32rr, CCMP32ri)
#undef FROM_TO
}
}
diff --git a/llvm/test/CodeGen/X86/apx/foldimmediate.mir b/llvm/test/CodeGen/X86/apx/foldimmediate.mir
index 5fd5ae9c1ca9f1..d17dcee7cb7a27 100644
--- a/llvm/test/CodeGen/X86/apx/foldimmediate.mir
+++ b/llvm/test/CodeGen/X86/apx/foldimmediate.mir
@@ -46,9 +46,9 @@ body: |
; CHECK-NEXT: NOOP implicit [[OR32ri]]
; CHECK-NEXT: [[XOR32ri:%[0-9]+]]:gr32 = XOR32ri [[COPY]], 81, implicit-def $eflags
; CHECK-NEXT: NOOP implicit [[XOR32ri]]
- ; CHECK-NEXT: TEST32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: CTEST32ri [[COPY]], 81, 2, 10, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit $eflags
- ; CHECK-NEXT: CMP32ri [[COPY]], 81, implicit-def $eflags
+ ; CHECK-NEXT: CCMP32ri [[COPY]], 81, 2, 10, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit $eflags
; CHECK-NEXT: [[ADC32ri:%[0-9]+]]:gr32 = ADC32ri [[COPY]], 81, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit [[ADC32ri]]
@@ -68,15 +68,15 @@ body: |
; CHECK-NEXT: NOOP implicit [[XOR64ri32_]]
; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64 = MOV32ri64 81
; CHECK-NEXT: NOOP implicit [[MOV32ri64_]]
- ; CHECK-NEXT: TEST64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: CTEST64ri32 [[COPY1]], 81, 2, 10, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit $eflags
; CHECK-NEXT: [[ADC64ri32_:%[0-9]+]]:gr64 = ADC64ri32 [[COPY1]], 81, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit [[ADC64ri32_]]
; CHECK-NEXT: [[SBB64ri32_:%[0-9]+]]:gr64 = SBB64ri32 [[COPY1]], 81, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit [[SBB64ri32_]]
- ; CHECK-NEXT: CMP64ri32 [[COPY1]], 81, implicit-def $eflags
+ ; CHECK-NEXT: CCMP64ri32 [[COPY1]], 81, 2, 10, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit $eflags
- ; CHECK-NEXT: CMP64rr [[SUBREG_TO_REG]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: CCMP64ri32 [[SUBREG_TO_REG]], 81, 2, 10, implicit-def $eflags, implicit $eflags
; CHECK-NEXT: NOOP implicit $eflags
%0 = MOV32ri 81
%1 = COPY $edi
@@ -95,10 +95,10 @@ body: |
%6 = XOR32rr %0, %1, implicit-def $eflags
NOOP implicit %6
- TEST32rr %0, %1, implicit-def $eflags
+ CTEST32rr %0, %1, 2, 10, implicit-def $eflags, implicit $eflags
NOOP implicit $eflags
- CMP32rr %1, %0, implicit-def $eflags
+ CCMP32rr %1, %0, 2, 10, implicit-def $eflags, implicit $eflags
NOOP implicit $eflags
%16 = ADC32rr %0, %1, implicit-def $eflags, implicit $eflags
@@ -127,7 +127,7 @@ body: |
%14 = COPY %7
NOOP implicit %14
- TEST64rr %8, %7, implicit-def $eflags
+ CTEST64rr %8, %7, 2, 10, implicit-def $eflags, implicit $eflags
NOOP implicit $eflags
%15 = ADC64rr %8, %7, implicit-def $eflags, implicit $eflags
@@ -136,8 +136,8 @@ body: |
%17 = SBB64rr %8, %7, implicit-def $eflags, implicit $eflags
NOOP implicit %17
- CMP64rr %8, %7, implicit-def $eflags
+ CCMP64rr %8, %7, 2, 10, implicit-def $eflags, implicit $eflags
NOOP implicit $eflags
- CMP64rr %7, %8, implicit-def $eflags
+ CCMP64rr %7, %8, 2, 10, implicit-def $eflags, implicit $eflags
NOOP implicit $eflags
...
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