[llvm] 8551454 - [RISCV] Rename $merge to $rd in Zvk* pseudoinstructions and patterns.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 15:35:46 PDT 2024
Author: Craig Topper
Date: 2024-03-25T15:27:30-07:00
New Revision: 8551454313233ecc70a329de0eb0064ecb675d50
URL: https://github.com/llvm/llvm-project/commit/8551454313233ecc70a329de0eb0064ecb675d50
DIFF: https://github.com/llvm/llvm-project/commit/8551454313233ecc70a329de0eb0064ecb675d50.diff
LOG: [RISCV] Rename $merge to $rd in Zvk* pseudoinstructions and patterns.
These instructions use the destination operand as a source, not
only as a passthru for mask/tail.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 617ca3242cc75f..80ba5452919695 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -181,13 +181,13 @@ class ZvkMxSet<string vd_lmul> {
}
class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
- Pseudo<(outs RetClass:$rd),
- (ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ Pseudo<(outs RetClass:$rd_wb),
+ (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = "$rd = $merge";
+ let Constraints = "$rd_wb = $rd";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
@@ -197,14 +197,14 @@ class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
class VPseudoBinaryNoMask_Zvk<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class> :
- Pseudo<(outs RetClass:$rd),
- (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1,
+ Pseudo<(outs RetClass:$rd_wb),
+ (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let Constraints = "$rd = $merge";
+ let Constraints = "$rd_wb = $rd";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
@@ -670,11 +670,11 @@ class VPatUnaryNoMask_Zvk<string intrinsic_name,
VReg result_reg_class,
VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
- (result_type result_reg_class:$merge),
+ (result_type result_reg_class:$rd),
(op2_type op2_reg_class:$rs2),
VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
- (result_type result_reg_class:$merge),
+ (result_type result_reg_class:$rd),
(op2_type op2_reg_class:$rs2),
GPR:$vl, sew, (XLenVT timm:$policy))>;
@@ -689,11 +689,11 @@ class VPatUnaryNoMask_VS_Zvk<string intrinsic_name,
VReg result_reg_class,
VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
- (result_type result_reg_class:$merge),
+ (result_type result_reg_class:$rd),
(op2_type op2_reg_class:$rs2),
VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_"#vs2_lmul.MX)
- (result_type result_reg_class:$merge),
+ (result_type result_reg_class:$rd),
(op2_type op2_reg_class:$rs2),
GPR:$vl, sew, (XLenVT timm:$policy))>;
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