[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads (PR #84965)

[Michael Maitland via llvm-commits]

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@@ -220,7 +220,8 @@ struct TypePairAndMemDesc {
            Align >= Other.Align &&
            // FIXME: This perhaps should be stricter, but the current legality
            // rules are written only considering the size.
-           MemTy.getSizeInBits() == Other.MemTy.getSizeInBits();
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michaelmaitland wrote:

We don't currently support a G_BITCAST between a scalar and a vector at the moment. I was using it as an example to show that if the types do not obviously match, then maybe it is a better idea to explicitly convert them into a form that does match using an instruction.

In the case of `ScalableEltTy == ScalarEltTy and MinNumElts > 1` I am suggesting that we disallow the load because the TypeSize does not match, and instead rely on an instruction to get us in a form where type size does match. My point is that it is possible but we should be explicit in making it possible. Vectors and scalars use different registers on RISC-V and it is likely that that "convert instruction" will make it easier to select a transfer from vector to scalar or scalar to vector if we need to do that.

https://github.com/llvm/llvm-project/pull/84965