[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads (PR #84965)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 12:59:03 PDT 2024
================
@@ -220,7 +220,8 @@ struct TypePairAndMemDesc {
Align >= Other.Align &&
// FIXME: This perhaps should be stricter, but the current legality
// rules are written only considering the size.
- MemTy.getSizeInBits() == Other.MemTy.getSizeInBits();
----------------
michaelmaitland wrote:
I think that it would be a good idea to restrict the types to match here. If we want to do loads across different types then we should have some opcode that "adjusts the type" like a bitcast:
```
%0(vscale x 2 x s8) = G_IMPLICIT_DEF
%1(vscale x 1 x s16 = G_BITCAST %0
...
```
https://github.com/llvm/llvm-project/pull/84965
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