[llvm] 25bcdab - [RISCV] Fix indentation and 80 columns in RISCVInstrInfoZvk.td. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 12:42:21 PDT 2024
Author: Craig Topper
Date: 2024-03-25T12:42:07-07:00
New Revision: 25bcdab47807d56ba8a06211348c5f44f030f407
URL: https://github.com/llvm/llvm-project/commit/25bcdab47807d56ba8a06211348c5f44f030f407
DIFF: https://github.com/llvm/llvm-project/commit/25bcdab47807d56ba8a06211348c5f44f030f407.diff
LOG: [RISCV] Fix indentation and 80 columns in RISCVInstrInfoZvk.td. NFC
I didn't fix all the 80 column errors just the ones in template
arguments.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index b4bd074b710179..67b2ad459360d3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -273,7 +273,8 @@ multiclass VPseudoVALU_VV_NoMask_Zvk<string Constraint = ""> {
}
}
-multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5, string Constraint = ""> {
+multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5,
+ string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
@@ -285,7 +286,8 @@ multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5, string Constraint
}
}
-multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5, string Constraint = ""> {
+multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5,
+ string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
@@ -668,14 +670,14 @@ foreach vtiToWti = AllWidenableIntVectors in {
//===----------------------------------------------------------------------===//
class VPatUnaryNoMask_Zvk<string intrinsic_name,
- string inst,
- string kind,
- ValueType result_type,
- ValueType op2_type,
- int sew,
- LMULInfo vlmul,
- VReg result_reg_class,
- VReg op2_reg_class> :
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op2_type,
+ int sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
@@ -686,15 +688,15 @@ class VPatUnaryNoMask_Zvk<string intrinsic_name,
GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatUnaryNoMask_VS_Zvk<string intrinsic_name,
- string inst,
- string kind,
- ValueType result_type,
- ValueType op2_type,
- int sew,
- LMULInfo vlmul,
- LMULInfo vs2_lmul,
- VReg result_reg_class,
- VReg op2_reg_class> :
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op2_type,
+ int sew,
+ LMULInfo vlmul,
+ LMULInfo vs2_lmul,
+ VReg result_reg_class,
+ VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
@@ -705,7 +707,7 @@ class VPatUnaryNoMask_VS_Zvk<string intrinsic_name,
GPR:$vl, sew, (XLenVT timm:$policy))>;
multiclass VPatUnaryV_V_NoMask_Zvk<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist> {
foreach vti = vtilist in
def : VPatUnaryNoMask_Zvk<intrinsic # "_vv", instruction, "VV",
vti.Vector, vti.Vector, vti.Log2SEW,
@@ -713,7 +715,7 @@ multiclass VPatUnaryV_V_NoMask_Zvk<string intrinsic, string instruction,
}
multiclass VPatUnaryV_S_NoMaskVectorCrypto<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist> {
foreach vti = vtilist in
foreach vti_vs2 = ZvkI32IntegerVectors<vti.LMul.MX>.vs2_types in
def : VPatUnaryNoMask_VS_Zvk<intrinsic # "_vs", instruction, "VS",
@@ -722,13 +724,13 @@ multiclass VPatUnaryV_S_NoMaskVectorCrypto<string intrinsic, string instruction,
}
multiclass VPatUnaryV_V_S_NoMask_Zvk<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist> {
defm : VPatUnaryV_V_NoMask_Zvk<intrinsic, instruction, vtilist>;
defm : VPatUnaryV_S_NoMaskVectorCrypto<intrinsic, instruction, vtilist>;
}
multiclass VPatBinaryV_VV_NoMask<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist> {
foreach vti = vtilist in
def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector,
@@ -737,7 +739,8 @@ multiclass VPatBinaryV_VV_NoMask<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VI_NoMask<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, Operand imm_type = tuimm5> {
+ list<VTypeInfo> vtilist,
+ Operand imm_type = tuimm5> {
foreach vti = vtilist in
def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT,
@@ -746,7 +749,8 @@ multiclass VPatBinaryV_VI_NoMask<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VI_NoMaskTU<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, Operand imm_type = tuimm5> {
+ list<VTypeInfo> vtilist,
+ Operand imm_type = tuimm5> {
foreach vti = vtilist in
def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VI_" # vti.LMul.MX,
vti.Vector, vti.Vector, XLenVT, vti.Log2SEW,
@@ -754,7 +758,7 @@ multiclass VPatBinaryV_VI_NoMaskTU<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VV_NoMaskTU<string intrinsic, string instruction,
- list<VTypeInfo> vtilist> {
+ list<VTypeInfo> vtilist> {
foreach vti = vtilist in
def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VV_" # vti.LMul.MX,
vti.Vector, vti.Vector, vti.Vector, vti.Log2SEW,
@@ -812,13 +816,14 @@ multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,
}
multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,
- string instruction2, list<VTypeInfo> vtilist>
+ string instruction2, list<VTypeInfo> vtilist>
: VPatBinaryV_VV<intrinsic, instruction, vtilist>,
VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;
multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,
- list<VTypeInfo> vtilist, Operand ImmType = uimm6>
+ list<VTypeInfo> vtilist,
+ Operand ImmType = uimm6>
: VPatBinaryV_VV<intrinsic, instruction, vtilist>,
VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
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