[llvm] 8b9c3b5 - Revert "[RISCV][GISEL] Add instruction select tests for G_VSCALE"
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 11:51:29 PDT 2024
Author: Michael Maitland
Date: 2024-03-25T11:50:57-07:00
New Revision: 8b9c3b57b158beeedf69810c2a546ab350a91e57
URL: https://github.com/llvm/llvm-project/commit/8b9c3b57b158beeedf69810c2a546ab350a91e57
DIFF: https://github.com/llvm/llvm-project/commit/8b9c3b57b158beeedf69810c2a546ab350a91e57.diff
LOG: Revert "[RISCV][GISEL] Add instruction select tests for G_VSCALE"
This reverts commit c00a5ab8c4be14f63735ec61c5c9245c233cbcfc. It is not
consistent with SelectionDAG.
Added:
Modified:
Removed:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
deleted file mode 100644
index 084d5531c4597b..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
+++ /dev/null
@@ -1,412 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select \
-# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: test_1_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_1_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_2_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_2_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 2
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_3_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_3_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_CONSTANT i32 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- $x11 = COPY %3(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %4:gprb(s32) = COPY $x10
- $x10 = COPY %4(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_4_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_4_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_8_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_8_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_16_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_16_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: $x10 = COPY [[SLLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_SHL %0, %1(s32)
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_40_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_40_s32
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s32)
- $x11 = COPY %1(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:gprb(s32) = COPY $x10
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_1_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_1_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_2_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_2_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 2
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_3_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_3_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY1]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_CONSTANT i32 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- $x11 = COPY %3(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %4:gprb(s32) = COPY $x10
- %5:gprb(s32) = G_READ_VLENB
- %6:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %5(s32)
- $x11 = COPY %6(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_4_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_4_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_8_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_8_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_READ_VLENB
- %2:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %1(s32)
- $x11 = COPY %2(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_16_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_16_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SLLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_SHL %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_40_s64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_40_s64
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY1]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s32)
- $x11 = COPY %1(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:gprb(s32) = COPY $x10
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
deleted file mode 100644
index 3e480e5b8d732a..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
+++ /dev/null
@@ -1,140 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select \
-# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: test_1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_1
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = G_READ_VLENB
- %1:gprb(s64) = G_CONSTANT i64 2
- %2:gprb(s64) = G_LSHR %0, %1(s64)
- $x10 = COPY %2(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_3
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_3
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = G_READ_VLENB
- %1:gprb(s64) = G_CONSTANT i64 3
- %2:gprb(s64) = G_LSHR %0, %1(s64)
- %3:gprb(s64) = G_CONSTANT i64 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s64)
- $x11 = COPY %3(s64)
- PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %4:gprb(s64) = COPY $x10
- $x10 = COPY %4(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_4
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = G_READ_VLENB
- %1:gprb(s64) = G_CONSTANT i64 1
- %2:gprb(s64) = G_LSHR %0, %1(s64)
- $x10 = COPY %2(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_8
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_8
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = G_READ_VLENB
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_16
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_16
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: $x10 = COPY [[SLLI]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = G_READ_VLENB
- %1:gprb(s64) = G_CONSTANT i64 1
- %2:gprb(s64) = G_SHL %0, %1(s64)
- $x10 = COPY %2(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_40
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_40
- ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s64) = G_READ_VLENB
- %1:gprb(s64) = G_CONSTANT i64 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s64)
- $x11 = COPY %1(s64)
- PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:gprb(s64) = COPY $x10
- $x10 = COPY %2(s64)
- PseudoRET implicit $x10
-
-...
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