[llvm] [RISCV][GlobalISel] Legalize Scalable Vector Loads (PR #84965)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 09:36:44 PDT 2024
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@@ -210,12 +210,12 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, s32, (XLen == 64 || ST.hasStdExtD()) ? s64 : s32)
.clampScalar(1, sXLen, sXLen);
- auto &LoadStoreActions =
- getActionDefinitionsBuilder({G_LOAD, G_STORE})
- .legalForTypesWithMemDesc({{s32, p0, s8, 8},
- {s32, p0, s16, 16},
- {s32, p0, s32, 32},
- {p0, p0, sXLen, XLen}});
+ auto &LoadStoreActions = getActionDefinitionsBuilder({G_LOAD, G_STORE})
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michaelmaitland wrote:
Should we do `lowerIfMemSizeNotByteSizePow2` like AArch64?
https://github.com/llvm/llvm-project/pull/84965
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