[llvm] [RISCV] Fix and refactor Zvk sched classes (PR #86519)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 08:50:48 PDT 2024
https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/86519
* Add scheduling information for VPseudoVWALU_VI.
* VPseudoVALU_V_NoMask_Zvk defines VPseudoUnaryV_V_NoMask_Zvk and read two vector operands. It should only read one vector operand. The read of the merge operand is already noted by ReadVMask (or forceReadMergeOp=true).
* VPseudoVALU_S_NoMask_Zvk defines VPseudoUnaryV_S_NoMask_Zvk and read two vector operands. It should only read one vector operand. The read of the merge operand is already noted by ReadVMask (or forceReadMergeOp=true).
* VPseudoUnaryV_V defines VPseudoUnaryV_V and read two vector operands. It should only read one vector operand. The read of the merge operand is already noted by ReadVMask (or forceReadMergeOp=true).
* Convert all other cases `Sched<[...]>` to the equivalent SchedUnary or SchedBinary.
>From 2543af49b143a460d7db50de2af8a9f8d8b52feb Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 25 Mar 2024 08:28:43 -0700
Subject: [PATCH] [RISCV] Fix and refactor Zvk sched classes
* Add scheduling information for VPseudoVWALU_VI.
* VPseudoVALU_V_NoMask_Zvk defines VPseudoUnaryV_V_NoMask_Zvk and read
two vector operands. It should only read one vector operand. The read
of the merge operand is already noted by ReadVMask (or forceReadMergeOp=true).
* VPseudoVALU_S_NoMask_Zvk defines VPseudoUnaryV_S_NoMask_Zvk and read
two vector operands. It should only read one vector operand. The read
of the merge operand is already noted by ReadVMask (or forceReadMergeOp=true).
* VPseudoUnaryV_V defines VPseudoUnaryV_V and read two vector operands.
It should only read one vector operand. The read of the merge operand is already
noted by ReadVMask (or forceReadMergeOp=true).
* Convert all other cases `Sched<[...]>` to the equivalent SchedUnary or
SchedBinary.
---
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 4 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 53 +++++++------------
2 files changed, 21 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 8be4c7741ca12b..4be5ee22f61a84 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2998,7 +2998,9 @@ multiclass VPseudoVWALU_VV_VX {
multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX {
foreach m = MxListW in {
- defm "" : VPseudoBinaryW_VI<ImmType, m>;
+ defm "" : VPseudoBinaryW_VI<ImmType, m>,
+ SchedUnary<"WriteVIWALUV", "ReadVIWALUV", m.MX,
+ forceMergeOpRead=true>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index b4bd074b710179..efd452ec2654e4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -237,22 +237,18 @@ multiclass VPseudoUnaryV_S_NoMask_Zvk<LMULInfo m, string Constraint = ""> {
multiclass VPseudoVALU_V_NoMask_Zvk<string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm "" : VPseudoUnaryV_V_NoMask_Zvk<m, Constraint>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
multiclass VPseudoVALU_S_NoMask_Zvk<string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm "" : VPseudoUnaryV_S_NoMask_Zvk<m, Constraint>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
@@ -264,63 +260,52 @@ multiclass VPseudoVALU_V_S_NoMask_Zvk<string Constraint = ""> {
multiclass VPseudoVALU_VV_NoMask_Zvk<string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm _VV : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m,
Constraint>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm _VI : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, ImmType, m,
Constraint>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5, string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm _VI : VPseudoBinaryNoMask<m.vrclass, m.vrclass, ImmType, m,
Constraint>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
multiclass VPseudoVALU_VV_NoMaskTU_Zvk<string Constraint = ""> {
foreach m = MxListVF4 in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm _VV : VPseudoBinaryNoMask<m.vrclass, m.vrclass, m.vrclass, m,
Constraint>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
multiclass VPseudoVCLMUL_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
- defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
-
defm "" : VPseudoBinaryV_VV<m>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX<m>,
- Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
+ SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
+ forceMergeOpRead=true>;
}
}
@@ -336,11 +321,9 @@ multiclass VPseudoUnaryV_V<LMULInfo m> {
multiclass VPseudoVALU_V {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
- defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
-
defm "" : VPseudoUnaryV_V<m>,
- Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
+ SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
+ forceMergeOpRead=true>;
}
}
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