[llvm] [SelectionDAG] Add more cases for UDIV and SDIV (PR #86452)

[Jay Foad via llvm-commits]

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@@ -979,7 +979,9 @@ KnownBits KnownBits::udiv(const KnownBits &LHS, const KnownBits &RHS,
   assert(!LHS.hasConflict() && !RHS.hasConflict());
   KnownBits Known(BitWidth);
 
-  if (LHS.isZero() || RHS.isZero()) {
+  // if LHS < RHS, then LHS / RHS is 0.
+  std::optional<bool> ult = KnownBits::ult(LHS, RHS);
+  if (LHS.isZero() || RHS.isZero() || (ult && *ult)) {
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jayfoad wrote:

Please split this into a separate patch with unit test coverage.

https://github.com/llvm/llvm-project/pull/86452