[llvm] [Xtensa] Implement base CallConvention. (PR #83280)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 23 17:13:28 PDT 2024
================
@@ -23,5 +24,139 @@
using namespace llvm;
+static inline const MachineInstrBuilder &
+addFrameReference(const MachineInstrBuilder &MIB, int FI) {
+ MachineInstr *MI = MIB;
+ MachineFunction &MF = *MI->getParent()->getParent();
+ MachineFrameInfo &MFFrame = MF.getFrameInfo();
+ const MCInstrDesc &MCID = MI->getDesc();
+ MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
+ if (MCID.mayLoad())
+ Flags |= MachineMemOperand::MOLoad;
+ if (MCID.mayStore())
+ Flags |= MachineMemOperand::MOStore;
+ int64_t Offset = 0;
+ Align Alignment = MFFrame.getObjectAlign(FI);
+
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI, Offset),
+ Flags, MFFrame.getObjectSize(FI), Alignment);
+ return MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
+}
+
XtensaInstrInfo::XtensaInstrInfo(const XtensaSubtarget &STI)
- : XtensaGenInstrInfo(), RI(STI), STI(STI) {}
+ : XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP),
+ RI(STI), STI(STI) {}
+
+/// Adjust SP by Amount bytes.
+void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const {
+ DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+
+ if (Amount == 0)
+ return;
+
+ MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
+ const TargetRegisterClass *RC = &Xtensa::ARRegClass;
+
+ // create virtual reg to store immediate
+ unsigned Reg = RegInfo.createVirtualRegister(RC);
+
+ if (isInt<8>(Amount)) // addi sp, sp, amount
+ BuildMI(MBB, I, DL, get(Xtensa::ADDI), Reg).addReg(SP).addImm(Amount);
+ else { // Expand immediate that doesn't fit in 12-bit.
----------------
s-barannikov wrote:
8 bit?
Missing braces around if.
https://github.com/llvm/llvm-project/pull/83280
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