[llvm] [Target][RISCV] Add HwMode support to subregister index size/offset. (PR #86368)

[Craig Topper via llvm-commits]

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@@ -90,16 +90,16 @@ def TestTarget : Target;
 // CHECK-LABEL: RegisterClass DRegs:
 
 // CHECK-LABEL: SubRegIndex ssub1:
-// CHECK:        Offset, Size: 16, 16
+// CHECK:        Offset, Size: { Default:16, 16 }
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topperc wrote:

I split the Offset and Size on different lines.

https://github.com/llvm/llvm-project/pull/86368