[llvm] add ucmp and scmp support to SelectionDAG (PR #85822)
Miguel Raz Guzmán Macedo via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 22 21:39:58 PDT 2024
https://github.com/miguelraz updated https://github.com/llvm/llvm-project/pull/85822
>From b1c548cc51b2b5d6e31f196167005d75ef128f41 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miguel=20Raz=20Guzm=C3=A1n=20Macedo?=
<miguelraz at ciencias.unam.mx>
Date: Tue, 19 Mar 2024 10:46:15 -0600
Subject: [PATCH 1/3] add ucmp and scmp support to SelectionDAG
---
llvm/include/llvm/CodeGen/ISDOpcodes.h | 5 +++++
llvm/include/llvm/CodeGen/TargetLowering.h | 4 ++++
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++++++
llvm/unittests/Analysis/ValueTrackingTest.cpp | 2 ++
4 files changed, 17 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 49d51a27e3c0f6..287919fca14905 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -676,6 +676,11 @@ enum NodeType {
UMIN,
UMAX,
+ /// [US]CMP - Three way integer comparison - returns -1, 0, or 1 if
+ /// Op1 < Op2, Op1 == Op2, Op1 > Op2, respectively.
+ SCMP,
+ UCMP,
+
/// Bitwise operators - logical and, logical or, logical xor.
AND,
OR,
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 2f164a460db843..0786fc798f5748 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5314,6 +5314,10 @@ class TargetLowering : public TargetLoweringBase {
/// method accepts integers as its arguments.
SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const;
+ /// Method for building the DAG expansion of ISD::[US]CMP. This
+ /// method accepts integers as its arguments.
+ SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const;
+
/// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
/// method accepts integers as its arguments.
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6f6ed4bd45027b..e12a451bd105e7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6704,6 +6704,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
VT.getVectorElementType() == MVT::i1)
return getNode(ISD::XOR, DL, VT, N1, N2);
break;
+ case ISD::UCMP:
+ case ISD::SCMP:
+ assert(VT.isInteger() && "This operator does not apply to FP types!");
+ assert(N1.getValueType() == N2.getValueType() &&
+ N1.getValueType() == VT && "Binary operator types must match");
+ break;
case ISD::MUL:
assert(VT.isInteger() && "This operator does not apply to FP types!");
assert(N1.getValueType() == N2.getValueType() &&
diff --git a/llvm/unittests/Analysis/ValueTrackingTest.cpp b/llvm/unittests/Analysis/ValueTrackingTest.cpp
index 6c6897d83a256e..e78cbb4cc2644b 100644
--- a/llvm/unittests/Analysis/ValueTrackingTest.cpp
+++ b/llvm/unittests/Analysis/ValueTrackingTest.cpp
@@ -891,6 +891,8 @@ TEST(ValueTracking, propagatesPoison) {
{true, "call i32 @llvm.smin.i32(i32 %x, i32 %y)", 0},
{true, "call i32 @llvm.umax.i32(i32 %x, i32 %y)", 0},
{true, "call i32 @llvm.umin.i32(i32 %x, i32 %y)", 0},
+ {true, "call i32 @llvm.scmp.i32.i32(i32 %x, i32 %y)", 0},
+ {true, "call i32 @llvm.ucmp.i32.i32(i32 %x, i32 %y)", 0},
{true, "call i32 @llvm.bitreverse.i32(i32 %x)", 0},
{true, "call i32 @llvm.bswap.i32(i32 %x)", 0},
{false, "call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt)", 0},
>From 585fc01750916cee4d3f0a5caa442e95e1ed6c86 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miguel=20Raz=20Guzm=C3=A1n=20Macedo?=
<miguelraz at ciencias.unam.mx>
Date: Tue, 19 Mar 2024 13:06:14 -0600
Subject: [PATCH 2/3] formatter borks #5
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e12a451bd105e7..3d5ed5249a23bb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6707,8 +6707,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::UCMP:
case ISD::SCMP:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match");
break;
case ISD::MUL:
assert(VT.isInteger() && "This operator does not apply to FP types!");
>From f7dcf6feaa2c01a42f18e2f39289cb7c3df0246c Mon Sep 17 00:00:00 2001
From: miguelraz <miguelraz at ciencias.unam.mx>
Date: Fri, 22 Mar 2024 22:39:42 -0600
Subject: [PATCH 3/3] attempt to write the first case ISD::SCMP logic to fold
in the constants
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3d5ed5249a23bb..beb152b419b68c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6706,9 +6706,22 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
break;
case ISD::UCMP:
case ISD::SCMP:
+ // FIX: This cast is clearly wrong
+ assert(cast<SignedInt>(N1.getValueType) && "This operator should have signed types");
assert(VT.isInteger() && "This operator does not apply to FP types!");
assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
"Binary operator types must match");
+ // FIX: This logic should probably go in a separate function to deduplicate it from ucmp. Suggestions?
+ if (N1C > N2C) {
+ // FIX: All of these casts are horrible, I couldn't find the proper way to fold the constants in
+ return cast<ConstantInt>(1);
+ }
+ if (N1C == N2C) {
+ return cast<ConstantInt>(0);
+ }
+ if (N1C < N2C) {
+ return cast<ConstantInt>(-1);
+ }
break;
case ISD::MUL:
assert(VT.isInteger() && "This operator does not apply to FP types!");
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