[llvm] [AArch64] Adjust ROBsize for Ampere1/Ampere1A (NFC) (PR #86330)

[Philipp Tomsich via llvm-commits]

https://github.com/ptomsich created https://github.com/llvm/llvm-project/pull/86330

To align more closely with common usage, we now use the size of the reorder-buffer for MicroOpBufferSize instead of the entries of the global micro-op scheduler.

>From 6abdd633b431454a47eb22b6b437b6485f4ac3a1 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: Fri, 22 Mar 2024 20:31:07 +0100
Subject: [PATCH] [AArch64] Adjust ROBsize for Ampere1/Ampere1A (NFC)

To align more closely with common usage, we now use the size of the
reorder-buffer for MicroOpBufferSize instead of the entries of the
global micro-op scheduler.
---
 llvm/lib/Target/AArch64/AArch64SchedAmpere1.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
index cf9f50c2784bbe..269f4ec5e5fb16 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
@@ -18,7 +18,7 @@
 
 def Ampere1Model : SchedMachineModel {
   let IssueWidth            =   4;  // 4-way decode and dispatch
-  let MicroOpBufferSize     = 174;  // micro-op re-order buffer size
+  let MicroOpBufferSize     = 192;  // re-order buffer size
   let LoadLatency           =   4;  // Optimistic load latency
   let MispredictPenalty     =  10;  // Branch mispredict penalty
   let LoopMicroOpBufferSize =  32;  // Instruction queue size