[llvm] [AArch64] Adjust ROBsize for Ampere1B (NFC) (PR #86331)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Philipp Tomsich (ptomsich)

<details>
<summary>Changes</summary>

To align more closely with common usage, we now use the size of the reorder-buffer for MicroOpBufferSize instead of the entries of the global micro-op scheduler.

---
Full diff: https://github.com/llvm/llvm-project/pull/86331.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
index 9c4f000cf351b2..67f8593f1577a3 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
@@ -18,7 +18,7 @@
 
 def Ampere1BModel : SchedMachineModel {
   let IssueWidth            =  12;  // Maximum micro-ops dispatch rate.
-  let MicroOpBufferSize     = 192;  // micro-op re-order buffer size
+  let MicroOpBufferSize     = 208;  // micro-op re-order buffer size
   let LoadLatency           =   3;  // Optimistic load latency
   let MispredictPenalty     =  10;  // Branch mispredict penalty
   let LoopMicroOpBufferSize =  32;  // Instruction queue size

``````````

</details>


https://github.com/llvm/llvm-project/pull/86331