[llvm] [AMDGPU] Add a trap lowering workaround for gfx11 (PR #85854)

[Emma Pilkington via llvm-commits]

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@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -o - -run-pass=legalizer %s | FileCheck -check-prefix=GCN %s
+
+---
+name: test_trap
+body: |
+  bb.0:
+    ; GCN-LABEL: name: test_trap
+    ; GCN: successors: %bb.2(0x80000000)
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; GCN-NEXT: [[C1:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
+    ; GCN-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1)
+    ; GCN-NEXT: S_TRAP 2
+    ; GCN-NEXT: [[S_SENDMSG_RTN_B32_:%[0-9]+]]:sreg_32 = S_SENDMSG_RTN_B32 128
+    ; GCN-NEXT: $ttmp2 = S_MOV_B32 $m0
+    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_SENDMSG_RTN_B32_]], 1023, implicit-def $scc
+    ; GCN-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], 1024, implicit-def $scc
+    ; GCN-NEXT: $m0 = S_MOV_B32 [[S_OR_B32_]]
+    ; GCN-NEXT: S_SENDMSG 1, implicit $exec, implicit $m0
+    ; GCN-NEXT: $m0 = S_MOV_B32 $ttmp2
+    ; GCN-NEXT: S_BRANCH %bb.2
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: .1:
+    ; GCN-NEXT: successors:
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1)
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: .2:
+    ; GCN-NEXT: successors: %bb.2(0x80000000)
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: S_SETHALT 5
+    ; GCN-NEXT: S_BRANCH %bb.2
+    %0:_(s8) = G_CONSTANT i8 0
+    %1:_(p1) = G_CONSTANT i64 0
+    G_STORE %0, %1 :: (store 1, addrspace 1)
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
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epilk wrote:

Noted, I'll rebase and update this when that patch lands.

https://github.com/llvm/llvm-project/pull/85854