[llvm] e64e15e - [RISCV] Move the RISCVSchedule.td include after RISCVRegisterInfo.td. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 22 11:45:44 PDT 2024
Author: Craig Topper
Date: 2024-03-22T11:42:12-07:00
New Revision: e64e15ee597370a9731fcba0b2b8a514f26125e7
URL: https://github.com/llvm/llvm-project/commit/e64e15ee597370a9731fcba0b2b8a514f26125e7
DIFF: https://github.com/llvm/llvm-project/commit/e64e15ee597370a9731fcba0b2b8a514f26125e7.diff
LOG: [RISCV] Move the RISCVSchedule.td include after RISCVRegisterInfo.td. NFC
Registers shouldn't depend on the scheduler, but a scheduler
predicate could depend on a register.
This would make it possible to move VLDSX0Pred out of the SiFive7
scheduler model to RISCVSchedule.td if another model needed it.
Added:
Modified:
llvm/lib/Target/RISCV/RISCV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 22736edc5f0720..9fb84efd5b6f26 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -24,8 +24,8 @@ include "RISCVSystemOperands.td"
// Registers, calling conventions, instruction descriptions.
//===----------------------------------------------------------------------===//
-include "RISCVSchedule.td"
include "RISCVRegisterInfo.td"
+include "RISCVSchedule.td"
include "RISCVCallingConv.td"
include "RISCVInstrInfo.td"
include "GISel/RISCVRegisterBanks.td"
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