[llvm] [RISCV] Add a tune feature to disable stripping W suffix (PR #86255)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> > > > > > For some implementations, instructions with W suffix would be less
> > > > > > costly as they only perform on 32 bits data. Though we may lose some
> > > > > > chances to compress.
> > > > > 
> > > > > 
> > > > > Do you know of a real implementation where this true?
> > > > 
> > > > 
> > > > Yes, this requirement is from hardware team actually and I didn't notice this stripping W suffix pass before.
> > > 
> > > 
> > > Is that for all 4 instructions(ADDW, ADDIW, SLLIW, MULW) that are in that pass or just MULW?
> > 
> > 
> > My intent is for all W instructions, not only multiply. Some low resources/low power consumption scenarios may need this too.
> 
> I was asking specifically about your hardware requirement. It's a bit questionable that MULW is in there. It's only useful with the Zcb extension and I think a cycle difference between MUL and MULW is more likely than ADD.

I can't say too much details here, sorry for that. All I can say is that hardware can do some performance/power optimizations if there are more W instructions.

> 
> I don't know if we're optimal on using W instructions so the existence of such hardware implies we might also need an "add W suffix" pass.

Yeah, I was thinking about the same thing and it's on my TODO list now. :-)

https://github.com/llvm/llvm-project/pull/86255