[llvm] Match fixed width ISD::AVGFLOORS + ISD::AVGCEILS patterns (PR #86222)

[Simon Pilgrim via llvm-commits]

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@@ -2529,18 +2529,29 @@ static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
 }
 
-// Attempt to form avgceilu(A, B) from (A | B) - ((A ^ B) >> 1)
-static SDValue combineFixedwidthToAVGCEILU(SDNode *N, SelectionDAG &DAG) {
+// Attempt to form avgceil(A, B) from (A | B) - ((A ^ B) >> 1)
+static SDValue combineFixedwidthToAVGCEIL(SDNode *N, SelectionDAG &DAG) {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue N0 = N->getOperand(0);
   EVT VT = N0.getValueType();
   SDLoc DL(N);
-  if (TLI.isOperationLegal(ISD::AVGCEILU, VT)) {
+  bool IsAVGCEILULegal = TLI.isOperationLegal(ISD::AVGCEILU, VT);
+  bool IsAVGCEILSLegal = TLI.isOperationLegal(ISD::AVGCEILS, VT);
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RKSimon wrote:

Don't bother doing this - just keep the ifs separate instead of nesting them - you're not gaining anything, Pull out the `SDValue A, B` line and you're done.

https://github.com/llvm/llvm-project/pull/86222