[lld] [WIP][lld] Support thumb PLTs for cortex-M (PR #86223)

[Peter Smith via llvm-commits]

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@@ -231,36 +231,68 @@ static void writePltHeaderLong(uint8_t *buf) {
 // The default PLT header requires the .got.plt to be within 128 Mb of the
 // .plt in the positive direction.
 void ARM::writePltHeader(uint8_t *buf) const {
-  // Use a similar sequence to that in writePlt(), the difference is the calling
-  // conventions mean we use lr instead of ip. The PLT entry is responsible for
-  // saving lr on the stack, the dynamic loader is responsible for reloading
-  // it.
-  const uint32_t pltData[] = {
-      0xe52de004, // L1: str lr, [sp,#-4]!
-      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
-      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
-      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
-  };
+  if (!config->armAlwaysThumb) {
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smithp35 wrote:

Maybe worth using a different selection criteria here for a couple of reasons:
* The Thumb sequences need Thumb-2 which isn't available on v6-m and v8-m devices.
* Thumb-2 PLTs can be used on CPUs with Arm. A colleague pointed out that it could be a net win in some cases as a Thumb-2 tail call to a PLT entry has to go to a Thumb to Arm interworking thunk with Arm only PLT entries.

https://github.com/llvm/llvm-project/pull/86223