[llvm] [Target] Move SubRegIdxRanges from MCSubtargetInfo to TargetInfo. (PR #86245)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 21 21:59:02 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/86245
I'm planning to add HwMode support to SubRegIdxRanges for RISC-V GPR pairs. The MC layer is currently unaware of the HwMode for registers and I'd like to keep it that way.
This information is not used by the MC layer so I think it is safe to move it.
>From fba5824016d81c05221b02a8cbdffc4d0532908d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 21 Mar 2024 13:20:11 -0700
Subject: [PATCH] [Target] Move SubRegIdxRanges from MCSubtargetInfo to
TargetInfo.
I'm planning to add HwMode support to SubRegIdxRanges for RISC-V GPR
pairs. The MC layer is currently unaware of the HwMode for registers
and I'd like to keep it that way.
This information is not used by the MC layer so I think it is safe
to move it.
---
.../include/llvm/CodeGen/TargetRegisterInfo.h | 31 ++++++++++++----
llvm/include/llvm/MC/MCRegisterInfo.h | 21 -----------
llvm/lib/CodeGen/TargetRegisterInfo.cpp | 36 +++++++++++--------
llvm/lib/MC/MCRegisterInfo.cpp | 12 -------
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +--
llvm/unittests/CodeGen/MFCommon.inc | 5 +--
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 29 +++++++--------
7 files changed, 65 insertions(+), 73 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 117d3f71829747..33c4c745c3416c 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -243,9 +243,20 @@ class TargetRegisterInfo : public MCRegisterInfo {
unsigned RegSize, SpillSize, SpillAlignment;
unsigned VTListOffset;
};
+
+ /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
+ /// index, -1 in any being invalid.
+ struct SubRegCoveredBits {
+ uint16_t Offset;
+ uint16_t Size;
+ };
+
private:
const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
const char *const *SubRegIndexNames; // Names of subreg indexes.
+ const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
+ // bit ranges array.
+
// Pointer to array of lane masks, one per sub-reg index.
const LaneBitmask *SubRegIndexLaneMasks;
@@ -256,12 +267,10 @@ class TargetRegisterInfo : public MCRegisterInfo {
unsigned HwMode;
protected:
- TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
- regclass_iterator RCB,
- regclass_iterator RCE,
- const char *const *SRINames,
- const LaneBitmask *SRILaneMasks,
- LaneBitmask CoveringLanes,
+ TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB,
+ regclass_iterator RCE, const char *const *SRINames,
+ const SubRegCoveredBits *SubIdxRanges,
+ const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes,
const RegClassInfo *const RCIs,
const MVT::SimpleValueType *const RCVTLists,
unsigned Mode = 0);
@@ -382,6 +391,16 @@ class TargetRegisterInfo : public MCRegisterInfo {
return SubRegIndexNames[SubIdx-1];
}
+ /// Get the size of the bit range covered by a sub-register index.
+ /// If the index isn't continuous, return the sum of the sizes of its parts.
+ /// If the index is used to access subregisters of different sizes, return -1.
+ unsigned getSubRegIdxSize(unsigned Idx) const;
+
+ /// Get the offset of the bit range covered by a sub-register index.
+ /// If an Offset doesn't make sense (the index isn't continuous, or is used to
+ /// access sub-registers at different offsets), return -1.
+ unsigned getSubRegIdxOffset(unsigned Idx) const;
+
/// Return a bitmask representing the parts of a register that are covered by
/// SubIdx \see LaneBitmask.
///
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index fb4d11ec1d4d16..c648ef20fa84c6 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -153,13 +153,6 @@ class MCRegisterInfo {
bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
};
- /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
- /// index, -1 in any being invalid.
- struct SubRegCoveredBits {
- uint16_t Offset;
- uint16_t Size;
- };
-
private:
const MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
@@ -176,8 +169,6 @@ class MCRegisterInfo {
const char *RegClassStrings; // Pointer to the class strings.
const uint16_t *SubRegIndices; // Pointer to the subreg lookup
// array.
- const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
- // bit ranges array.
unsigned NumSubRegIndices; // Number of subreg indices.
const uint16_t *RegEncodingTable; // Pointer to array of register
// encodings.
@@ -278,7 +269,6 @@ class MCRegisterInfo {
const int16_t *DL, const LaneBitmask *RUMS,
const char *Strings, const char *ClassStrings,
const uint16_t *SubIndices, unsigned NumIndices,
- const SubRegCoveredBits *SubIdxRanges,
const uint16_t *RET) {
Desc = D;
NumRegs = NR;
@@ -294,7 +284,6 @@ class MCRegisterInfo {
NumRegUnits = NRU;
SubRegIndices = SubIndices;
NumSubRegIndices = NumIndices;
- SubRegIdxRanges = SubIdxRanges;
RegEncodingTable = RET;
// Initialize DWARF register mapping variables
@@ -387,16 +376,6 @@ class MCRegisterInfo {
/// otherwise.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
- /// Get the size of the bit range covered by a sub-register index.
- /// If the index isn't continuous, return the sum of the sizes of its parts.
- /// If the index is used to access subregisters of different sizes, return -1.
- unsigned getSubRegIdxSize(unsigned Idx) const;
-
- /// Get the offset of the bit range covered by a sub-register index.
- /// If an Offset doesn't make sense (the index isn't continuous, or is used to
- /// access sub-registers at different offsets), return -1.
- unsigned getSubRegIdxOffset(unsigned Idx) const;
-
/// Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(MCRegister RegNo) const {
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index c9503fcb77bb21..4120c74c23b193 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -50,20 +50,16 @@ static cl::opt<unsigned>
"high compile time cost in global splitting."),
cl::init(5000));
-TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
- regclass_iterator RCB, regclass_iterator RCE,
- const char *const *SRINames,
- const LaneBitmask *SRILaneMasks,
- LaneBitmask SRICoveringLanes,
- const RegClassInfo *const RCIs,
- const MVT::SimpleValueType *const RCVTLists,
- unsigned Mode)
- : InfoDesc(ID), SubRegIndexNames(SRINames),
- SubRegIndexLaneMasks(SRILaneMasks),
- RegClassBegin(RCB), RegClassEnd(RCE),
- CoveringLanes(SRICoveringLanes),
- RCInfos(RCIs), RCVTLists(RCVTLists), HwMode(Mode) {
-}
+TargetRegisterInfo::TargetRegisterInfo(
+ const TargetRegisterInfoDesc *ID, regclass_iterator RCB,
+ regclass_iterator RCE, const char *const *SRINames,
+ const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks,
+ LaneBitmask SRICoveringLanes, const RegClassInfo *const RCIs,
+ const MVT::SimpleValueType *const RCVTLists, unsigned Mode)
+ : InfoDesc(ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),
+ SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),
+ CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),
+ HwMode(Mode) {}
TargetRegisterInfo::~TargetRegisterInfo() = default;
@@ -596,6 +592,18 @@ bool TargetRegisterInfo::getCoveringSubRegIndexes(
return BestIdx;
}
+unsigned TargetRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
+ assert(Idx && Idx < getNumSubRegIndices() &&
+ "This is not a subregister index");
+ return SubRegIdxRanges[Idx].Size;
+}
+
+unsigned TargetRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
+ assert(Idx && Idx < getNumSubRegIndices() &&
+ "This is not a subregister index");
+ return SubRegIdxRanges[Idx].Offset;
+}
+
Register
TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
const MachineRegisterInfo *MRI) const {
diff --git a/llvm/lib/MC/MCRegisterInfo.cpp b/llvm/lib/MC/MCRegisterInfo.cpp
index a2c1737e2964f1..334655616d8dbb 100644
--- a/llvm/lib/MC/MCRegisterInfo.cpp
+++ b/llvm/lib/MC/MCRegisterInfo.cpp
@@ -57,18 +57,6 @@ unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,
return 0;
}
-unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
- assert(Idx && Idx < getNumSubRegIndices() &&
- "This is not a subregister index");
- return SubRegIdxRanges[Idx].Size;
-}
-
-unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
- assert(Idx && Idx < getNumSubRegIndices() &&
- "This is not a subregister index");
- return SubRegIdxRanges[Idx].Offset;
-}
-
int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 79a7d1cf66c4d3..245731ad5fc7c9 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -363,8 +363,8 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
for (auto &Row : SubRegFromChannelTable)
Row.fill(AMDGPU::NoSubRegister);
for (unsigned Idx = 1; Idx < getNumSubRegIndices(); ++Idx) {
- unsigned Width = AMDGPUSubRegIdxRanges[Idx].Size / 32;
- unsigned Offset = AMDGPUSubRegIdxRanges[Idx].Offset / 32;
+ unsigned Width = getSubRegIdxSize(Idx) / 32;
+ unsigned Offset = getSubRegIdxOffset(Idx) / 32;
assert(Width < SubRegFromChannelTableWidthMap.size());
Width = SubRegFromChannelTableWidthMap[Width];
if (Width == 0)
diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc
index 7de7eabdd1f604..1997e805229757 100644
--- a/llvm/unittests/CodeGen/MFCommon.inc
+++ b/llvm/unittests/CodeGen/MFCommon.inc
@@ -23,9 +23,10 @@ class BogusRegisterInfo : public TargetRegisterInfo {
public:
BogusRegisterInfo()
: TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses,
- nullptr, nullptr, LaneBitmask(~0u), nullptr, nullptr) {
+ nullptr, nullptr, nullptr, LaneBitmask(~0u), nullptr,
+ nullptr) {
InitMCRegisterInfo(nullptr, 0, 0, 0, nullptr, 0, nullptr, 0, nullptr,
- nullptr, nullptr, nullptr, nullptr, 0, nullptr, nullptr);
+ nullptr, nullptr, nullptr, nullptr, 0, nullptr);
}
const MCPhysReg *
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index d074e31c624588..c4fc1930488cf7 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -955,16 +955,6 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
SubRegIdxSeqs.emit(OS, printSubRegIndex);
OS << "};\n\n";
- // Emit the table of sub-register index sizes.
- OS << "extern const MCRegisterInfo::SubRegCoveredBits " << TargetName
- << "SubRegIdxRanges[] = {\n";
- OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
- for (const auto &Idx : SubRegIndices) {
- OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
- << Idx.getName() << "\n";
- }
- OS << "};\n\n";
-
// Emit the string table.
RegStrings.layout();
RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
@@ -1101,8 +1091,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
<< TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
<< TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
<< (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
- << TargetName << "SubRegIdxRanges, " << TargetName
- << "RegEncodingTable);\n\n";
+ << TargetName << "RegEncodingTable);\n\n";
EmitRegMapping(OS, Regs, false);
@@ -1253,6 +1242,16 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
}
OS << "\" };\n\n";
+ // Emit the table of sub-register index sizes.
+ OS << "static const TargetRegisterInfo::SubRegCoveredBits "
+ "SubRegIdxRangeTable[] = {\n";
+ OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
+ for (const auto &Idx : SubRegIndices) {
+ OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
+ << Idx.getName() << "\n";
+ }
+ OS << "};\n\n";
+
// Emit SubRegIndex lane masks, including 0.
OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n "
"LaneBitmask::getAll(),\n";
@@ -1634,8 +1633,6 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "extern const char " << TargetName << "RegClassStrings[];\n";
OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
- OS << "extern const MCRegisterInfo::SubRegCoveredBits " << TargetName
- << "SubRegIdxRanges[];\n";
OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
EmitRegMappingTables(OS, Regs, true);
@@ -1646,7 +1643,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
" unsigned PC, unsigned HwMode)\n"
<< " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n"
- << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n"
+ << " SubRegIndexNameTable, SubRegIdxRangeTable, "
+ "SubRegIndexLaneMaskTable,\n"
<< " ";
printMask(OS, RegBank.CoveringLanes);
OS << ", RegClassInfos, VTLists, HwMode) {\n"
@@ -1661,7 +1659,6 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< " " << TargetName << "RegClassStrings,\n"
<< " " << TargetName << "SubRegIdxLists,\n"
<< " " << SubRegIndicesSize + 1 << ",\n"
- << " " << TargetName << "SubRegIdxRanges,\n"
<< " " << TargetName << "RegEncodingTable);\n\n";
EmitRegMapping(OS, Regs, true);
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