[llvm] 7564566 - Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 21 17:25:56 PDT 2024
Author: Jonas Paulsson
Date: 2024-03-21T20:24:57-04:00
New Revision: 7564566779eb07e9daf41a351b09cf7607871845
URL: https://github.com/llvm/llvm-project/commit/7564566779eb07e9daf41a351b09cf7607871845
DIFF: https://github.com/llvm/llvm-project/commit/7564566779eb07e9daf41a351b09cf7607871845.diff
LOG: Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"
- The check is now actually done in both PEI and the MachineVerifier.
- More .mir tests trivially updated with "adjustsStack: true" as needed.
Added:
llvm/test/MachineVerifier/test_adjustsstack.mir
Modified:
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
llvm/test/CodeGen/SystemZ/int-cmp-56.mir
llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
llvm/test/CodeGen/X86/callbr-asm-kill.mir
llvm/test/CodeGen/X86/late-remat-update.mir
llvm/test/CodeGen/X86/limit-split-cost.mir
llvm/test/CodeGen/X86/regalloc-copy-hints.mir
llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir
llvm/test/DebugInfo/X86/live-debug-vars-intervals.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index c69d36fc7fdd60..005efe48ac0c3e 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -3697,6 +3697,9 @@ void MachineVerifier::verifyStackFrame() {
if (I.getOpcode() == FrameSetupOpcode) {
if (BBState.ExitIsSetup)
report("FrameSetup is after another FrameSetup", &I);
+ if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
+ report("AdjustsStack not set in presence of a frame pseudo "
+ "instruction.", &I);
BBState.ExitValue -= TII->getFrameTotalSize(I);
BBState.ExitIsSetup = true;
}
@@ -3712,6 +3715,9 @@ void MachineVerifier::verifyStackFrame() {
errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
<< AbsSPAdj << ">.\n";
}
+ if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
+ report("AdjustsStack not set in presence of a frame pseudo "
+ "instruction.", &I);
BBState.ExitValue += Size;
BBState.ExitIsSetup = false;
}
diff --git a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
index 9040937d027df4..1592c86e267f5c 100644
--- a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
+++ b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir
@@ -3,6 +3,8 @@
---
name: func
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
body: |
bb.0:
liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6
diff --git a/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir b/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
index aa94a03786f54a..47aa34e3c01156 100644
--- a/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
+++ b/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
@@ -22,6 +22,7 @@
name: inst_stores_to_dead_spill_implicit_def_impdef
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0:
@@ -59,6 +60,7 @@ body: |
name: inst_stores_to_dead_spill_movimm_impdef
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0:
diff --git a/llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir b/llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
index e5395b20afd426..a5d74ef75f0a0a 100644
--- a/llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
+++ b/llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
@@ -4,6 +4,8 @@
---
name: widget
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
jumpTable:
kind: label-
diff erence32
entries:
diff --git a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
index 3616d617f84a0d..5ef8a94eeaa7c6 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
@@ -8,6 +8,8 @@
---
name: restore_undef_copy_use
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
machineFunctionInfo:
maxKernArgAlign: 1
isEntryFunction: true
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir b/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
index bdd89a9077900e..dde84af57ed253 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
@@ -13,6 +13,7 @@
name: greedy_fail_alloc_sgpr1024_spill
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
machineFunctionInfo:
explicitKernArgSize: 16
diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir b/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
index 2ccc24152a9f0b..fdfc9b043cc9d2 100644
--- a/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
@@ -24,6 +24,7 @@ registers:
- { id: 10, class: sreg_64_xexec, preferred-register: '$vcc' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo:
maxKernArgAlign: 1
diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
index c0d199920bd94e..09037709d51d8b 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
@@ -181,6 +181,8 @@ legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
liveins:
- { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$vgpr1', virtual-reg: '%1' }
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
index efbdbca9da6b7f..c6ccbd99bf8902 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
@@ -78,6 +78,7 @@
name: sgpr_spill_wrong_stack_id
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir b/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
index 355829825146df..f8ec6bb5d943f7 100644
--- a/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
+++ b/llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
@@ -21,6 +21,7 @@
name: kernel
tracksRegLiveness: true
frameInfo:
+ adjustsStack: true
hasCalls: true
machineFunctionInfo:
isEntryFunction: true
diff --git a/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir b/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
index 3d9db687ffa15a..6659e953237692 100644
--- a/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
@@ -20,6 +20,7 @@ name: undef_identity_copy
tracksRegLiveness: true
frameInfo:
maxAlignment: 4
+ adjustsStack: true
hasCalls: true
machineFunctionInfo:
isEntryFunction: true
diff --git a/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir b/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
index 5c59566247d892..b4bbb9be8ae405 100644
--- a/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
+++ b/llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
@@ -86,6 +86,8 @@
---
name: main
exposesReturnsTwice: true
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, name: P0, size: 80, alignment: 8, local-offset: -80 }
- { id: 1, name: jb1, size: 160, alignment: 8, local-offset: -240 }
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
index 67f4dd72ea0b2d..9468b18bf8e47e 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
@@ -135,7 +135,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
diff --git a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
index 3b308ce3d0d24c..adeec15b175523 100644
--- a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
+++ b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
@@ -25,6 +25,8 @@
name: autogen_SD21418
alignment: 4
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
registers:
- { id: 0, class: vr128bit }
- { id: 1, class: vr128bit }
diff --git a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
index 7ff7d9b8b7094a..197c3d8551fc38 100644
--- a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
+++ b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
@@ -157,6 +157,7 @@ registers:
- { id: 129, class: grx32bit }
- { id: 130, class: fp64bit }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0:
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-56.mir b/llvm/test/CodeGen/SystemZ/int-cmp-56.mir
index e52fd44ae47db9..3e00b6065eb908 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-56.mir
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-56.mir
@@ -48,6 +48,7 @@ liveins:
- { reg: '$r2d', virtual-reg: '%0' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
@@ -125,6 +126,7 @@ liveins:
- { reg: '$r2d', virtual-reg: '%0' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
@@ -202,6 +204,7 @@ liveins:
- { reg: '$r2d', virtual-reg: '%0' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
@@ -279,6 +282,7 @@ liveins:
- { reg: '$r2d', virtual-reg: '%0' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
index f709b70ff1b798..bf5855010bf90b 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
@@ -49,6 +49,8 @@ body: |
---
name: segfault
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
liveins: []
body: |
; CHECK-LABEL: name: segfault
diff --git a/llvm/test/CodeGen/X86/callbr-asm-kill.mir b/llvm/test/CodeGen/X86/callbr-asm-kill.mir
index 86c58c4715ed77..0dded37c97afa6 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-kill.mir
+++ b/llvm/test/CodeGen/X86/callbr-asm-kill.mir
@@ -45,6 +45,7 @@ liveins:
- { reg: '$rsi', virtual-reg: '%3' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/CodeGen/X86/late-remat-update.mir b/llvm/test/CodeGen/X86/late-remat-update.mir
index 84a78f84728cac..dd4e99c6df1418 100644
--- a/llvm/test/CodeGen/X86/late-remat-update.mir
+++ b/llvm/test/CodeGen/X86/late-remat-update.mir
@@ -66,6 +66,7 @@ registers:
liveins:
- { reg: '$edi', virtual-reg: '%0' }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.entry:
diff --git a/llvm/test/CodeGen/X86/limit-split-cost.mir b/llvm/test/CodeGen/X86/limit-split-cost.mir
index 6f5329e5b332a0..7ec0404e0f737c 100644
--- a/llvm/test/CodeGen/X86/limit-split-cost.mir
+++ b/llvm/test/CodeGen/X86/limit-split-cost.mir
@@ -86,6 +86,7 @@ registers:
liveins:
- { reg: '$edi', virtual-reg: '%0' }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.entry:
diff --git a/llvm/test/CodeGen/X86/regalloc-copy-hints.mir b/llvm/test/CodeGen/X86/regalloc-copy-hints.mir
index 13b5a541fa2282..d09bcd6a6b402d 100644
--- a/llvm/test/CodeGen/X86/regalloc-copy-hints.mir
+++ b/llvm/test/CodeGen/X86/regalloc-copy-hints.mir
@@ -103,6 +103,7 @@ registers:
- { id: 82, class: gr32 }
frameInfo:
maxAlignment: 4
+ adjustsStack: true
hasCalls: true
fixedStack:
- { id: 0, size: 4, alignment: 4, stack-id: default, isImmutable: true }
diff --git a/llvm/test/CodeGen/X86/statepoint-fastregalloc.mir b/llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
index 02c9310673006f..8bac14018a7dd3 100644
--- a/llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
+++ b/llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
@@ -6,6 +6,8 @@
---
name: test_relocate
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
body: |
bb.0.entry:
liveins: $rdi
@@ -25,6 +27,8 @@ body: |
---
name: test_relocate_multi_regmasks
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
body: |
bb.0.entry:
liveins: $rdi
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
index 11968f17c70a3e..5f05270729fdec 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
@@ -231,7 +231,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
index aae2f3870138c0..cf9128260f1962 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir
@@ -398,7 +398,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
index 87f5f0f96c505d..fcebc69d9b2e35 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
@@ -175,7 +175,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 4
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
index 49253968fcca58..8bb39a03f7e368 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
@@ -226,7 +226,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 4
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
index 858ff3f1888b98..da651039ce21e0 100644
--- a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
+++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
@@ -172,7 +172,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 4
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-folding.mir b/llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
index e24d5e8af1f553..d40a9a06d1620e 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
@@ -114,7 +114,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 8
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
index cece656d08978c..5ebd1a89ae9217 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
@@ -100,6 +100,7 @@ registers:
- { id: 38, class: gr8 }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
index f0af9380404831..b0bff30c4c8206 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
@@ -87,6 +87,7 @@ liveins:
- { reg: '$edi', virtual-reg: '%0' }
- { reg: '$xmm0', virtual-reg: '%1' }
frameInfo:
+ adjustsStack: true
hasCalls: true
body: |
bb.0.if.then:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
index 51d3f7e1a6a4ef..d73d8a37590615 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
@@ -97,6 +97,7 @@ liveins:
- { reg: '$esi', virtual-reg: '%4' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
index bc1c7ebac6cef8..6460263c6025a8 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
@@ -106,6 +106,7 @@ liveins:
- { reg: '$rsi', virtual-reg: '%5' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
index d59333e73fbce8..68c9bf6c89dde2 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
@@ -70,6 +70,7 @@ liveins:
- { reg: '$esi', virtual-reg: '%2' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
index ab2647d3b45a15..cf17af4ba43080 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
@@ -71,6 +71,7 @@ liveins:
- { reg: '$esi', virtual-reg: '%2' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
index 0fe80980e4e6ff..cb35bd892eea58 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
@@ -65,6 +65,7 @@ liveins:
- { reg: '$esi', virtual-reg: '%2' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
index 2a031b295a1e11..61dcec49b74cd7 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
@@ -94,6 +94,7 @@ liveins:
- { reg: '$esi', virtual-reg: '%2' }
frameInfo:
maxAlignment: 1
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
index 47a7b460e43ef0..e80ed2e3e8eb3f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
@@ -106,6 +106,7 @@ liveins:
- { reg: '$rdi', virtual-reg: '%15' }
frameInfo:
maxAlignment: 8
+ adjustsStack: true
hasCalls: true
stack:
- { id: 0, size: 8, alignment: 8 }
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
index 3e806e43ca9e67..6dbd2cd4faa712 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
@@ -113,6 +113,7 @@ liveins:
- { reg: '$rdi', virtual-reg: '%2' }
- { reg: '$esi', virtual-reg: '%4' }
frameInfo:
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir b/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
index 35ab906efc9042..5df70096e9305d 100644
--- a/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
@@ -72,6 +72,8 @@
name: fn2
alignment: 4
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
index 3cb9da8fdfe3b8..4d48774a78dd71 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
@@ -116,7 +116,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
index 35d12b52af896c..e618f48f527b88 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
@@ -114,7 +114,7 @@ frameInfo:
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
- adjustsStack: false
+ adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 4294967295
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir
index 037306a2ca95ed..42ee73dde96592 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir
@@ -100,6 +100,7 @@ liveins:
- { reg: '$rdi', virtual-reg: '%2' }
- { reg: '$esi', virtual-reg: '%4' }
frameInfo:
+ adjustsStack: true
hasCalls: true
machineFunctionInfo: {}
body: |
diff --git a/llvm/test/DebugInfo/X86/live-debug-vars-intervals.mir b/llvm/test/DebugInfo/X86/live-debug-vars-intervals.mir
index c5b6d7381ace9a..3beaf8996e4f07 100644
--- a/llvm/test/DebugInfo/X86/live-debug-vars-intervals.mir
+++ b/llvm/test/DebugInfo/X86/live-debug-vars-intervals.mir
@@ -99,6 +99,8 @@
---
name: f1
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, name: x.addr, type: default, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
@@ -127,6 +129,8 @@ body: |
---
name: f2
tracksRegLiveness: true
+frameInfo:
+ adjustsStack: true
stack:
- { id: 0, name: x.addr, type: default, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
diff --git a/llvm/test/MachineVerifier/test_adjustsstack.mir b/llvm/test/MachineVerifier/test_adjustsstack.mir
new file mode 100644
index 00000000000000..d333737e000cc6
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_adjustsstack.mir
@@ -0,0 +1,26 @@
+# RUN: not --crash llc -o - -start-before=twoaddressinstruction -verify-machineinstrs %s 2>&1 \
+# RUN: | FileCheck %s
+# REQUIRES: aarch64-registered-target
+--- |
+ target triple = "aarch64-unknown-linux"
+ declare i32 @bar(i32) nounwind
+ define i32 @foo() nounwind {
+ call i32 @bar(i32 0)
+ ret i32 0
+ }
+...
+---
+name: foo
+registers:
+ - { id: 0, class: gpr32 }
+body: |
+ bb.0 (%ir-block.0):
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %0 = COPY $wzr
+ $w0 = COPY %0
+ BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $w0 = COPY killed %0
+ RET_ReallyLR implicit $w0
+...
+# CHECK-LABEL: Bad machine code: AdjustsStack not set in presence of a frame pseudo instruction.
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