[llvm] [RISCV][GISEL] Legalize, regbank select, and instruction select G_ZEXT, G_SEXT, G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP (PR #85938)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff f872043e055f4163c3c4b1b86ca0354490174987 9322096dea44dbc12b5031a3afb870ac68d27e8f -- llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp llvm/lib/CodeGen/LowLevelTypeUtils.cpp llvm/lib/CodeGen/MachineVerifier.cpp llvm/lib/CodeGen/RegisterBankInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 1681cd1018..0f66890a19 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -522,7 +522,7 @@ bool RISCVLegalizerInfo::legalizeExt(MachineInstr &MI,
 
   LLT DstTy = MRI.getType(Dst);
   LLT SrcTy = MRI.getType(Src);
-  
+
   int64_t ExtTrueVal =
       Opc == TargetOpcode::G_ZEXT || Opc == TargetOpcode::G_ANYEXT ? 1 : -1;
   LLT DstEltTy = DstTy.getElementType();

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https://github.com/llvm/llvm-project/pull/85938