[llvm] Revert "[AMDGPU] MCExpr-ify MC layer kernel descriptor" (PR #86151)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 21 09:47:50 PDT 2024
github-actions[bot] wrote:
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``````````bash
git-clang-format --diff 69429276098df2f2cf67dcab1c96ce8f56280c11 ddabe09c4e14b5cd58d6047f98f5281257e8b3ac -- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
``````````
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<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 72e8b59e0a..6fb9eb8c99 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -428,9 +428,9 @@ uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
return KernelCodeProperties;
}
-amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
- const MachineFunction &MF,
- const SIProgramInfo &PI) const {
+amdhsa::kernel_descriptor_t
+AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(const MachineFunction &MF,
+ const SIProgramInfo &PI) const {
const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
const Function &F = MF.getFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
@@ -455,7 +455,7 @@ amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
assert(STM.hasGFX90AInsts() || CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0);
if (STM.hasGFX90AInsts())
KernelDescriptor.compute_pgm_rsrc3 =
- CurrentProgramInfo.ComputePGMRSrc3GFX90A;
+ CurrentProgramInfo.ComputePGMRSrc3GFX90A;
if (AMDGPU::hasKernargPreload(STM))
KernelDescriptor.kernarg_preload =
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
index 79326cd3d3..beca183797 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -75,9 +75,9 @@ private:
uint16_t getAmdhsaKernelCodeProperties(
const MachineFunction &MF) const;
- amdhsa::kernel_descriptor_t getAmdhsaKernelDescriptor(
- const MachineFunction &MF,
- const SIProgramInfo &PI) const;
+ amdhsa::kernel_descriptor_t
+ getAmdhsaKernelDescriptor(const MachineFunction &MF,
+ const SIProgramInfo &PI) const;
void initTargetStreamer(Module &M);
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 5297054796..aed271a366 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5564,8 +5564,8 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
return Error(IDRange.Start, "directive requires gfx10+", IDRange);
EnableWavefrontSize32 = Val;
PARSE_BITS_ENTRY(KD.kernel_code_properties,
- KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
- Val, ValRange);
+ KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Val,
+ ValRange);
} else if (ID == ".amdhsa_uses_dynamic_stack") {
PARSE_BITS_ENTRY(KD.kernel_code_properties,
KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, Val, ValRange);
@@ -5664,27 +5664,28 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
} else if (ID == ".amdhsa_fp16_overflow") {
if (IVersion.Major < 9)
return Error(IDRange.Start, "directive requires gfx9+", IDRange);
- PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL, Val,
- ValRange);
+ PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+ COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL, Val, ValRange);
} else if (ID == ".amdhsa_tg_split") {
if (!isGFX90A())
return Error(IDRange.Start, "directive requires gfx90a+", IDRange);
- PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Val,
- ValRange);
+ PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
+ Val, ValRange);
} else if (ID == ".amdhsa_workgroup_processor_mode") {
if (IVersion.Major < 10)
return Error(IDRange.Start, "directive requires gfx10+", IDRange);
- PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Val,
- ValRange);
+ PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+ COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Val, ValRange);
} else if (ID == ".amdhsa_memory_ordered") {
if (IVersion.Major < 10)
return Error(IDRange.Start, "directive requires gfx10+", IDRange);
- PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Val,
- ValRange);
+ PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+ COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Val, ValRange);
} else if (ID == ".amdhsa_forward_progress") {
if (IVersion.Major < 10)
return Error(IDRange.Start, "directive requires gfx10+", IDRange);
- PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS, Val,
+ PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+ COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS, Val,
ValRange);
} else if (ID == ".amdhsa_shared_vgpr_count") {
if (IVersion.Major < 10 || IVersion.Major >= 12)
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
index 4742b0b3e5..0cf7c8ea9e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -323,8 +323,7 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
<< KD.private_segment_fixed_size << '\n';
OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
- PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
if (!hasArchitectedFlatScratch(STI))
@@ -332,17 +331,14 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
- PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
- kernel_code_properties,
+ PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
- PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
- kernel_code_properties,
+ PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
- PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
- kernel_code_properties,
+ PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
if (!hasArchitectedFlatScratch(STI))
PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
@@ -358,8 +354,7 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
if (IVersion.Major >= 10)
- PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
- kernel_code_properties,
+ PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
@@ -370,20 +365,15 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
: ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
- PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
- PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
- PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
- PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
- PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
// These directives are required.
@@ -391,10 +381,12 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
if (AMDGPU::isGFX90A(STI))
- OS << "\t\t.amdhsa_accum_offset " <<
- (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3,
- amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
- << '\n';
+ OS << "\t\t.amdhsa_accum_offset "
+ << (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3,
+ amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) +
+ 1) *
+ 4
+ << '\n';
if (!ReserveVCC)
OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
@@ -411,17 +403,13 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
break;
}
- PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
- PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
- PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
- PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
if (IVersion.Major < 12) {
PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, compute_pgm_rsrc1,
@@ -430,22 +418,17 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE);
}
if (IVersion.Major >= 9)
- PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
if (AMDGPU::isGFX90A(STI))
- PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
- compute_pgm_rsrc3,
+ PRINT_FIELD(OS, ".amdhsa_tg_split", KD, compute_pgm_rsrc3,
amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
if (IVersion.Major >= 10) {
- PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
- PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
- PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
- compute_pgm_rsrc1,
+ PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
}
if (IVersion.Major >= 10 && IVersion.Major < 12) {
@@ -456,27 +439,20 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
PRINT_FIELD(OS, ".amdhsa_round_robin_scheduling", KD, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN);
PRINT_FIELD(
- OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
- compute_pgm_rsrc2,
+ OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
- PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
PRINT_FIELD(
- OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
- compute_pgm_rsrc2,
+ OS, ".amdhsa_exception_fp_ieee_div_zero", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
- PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
- PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
- PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
- PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
- compute_pgm_rsrc2,
+ PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
#undef PRINT_FIELD
@@ -872,12 +848,13 @@ void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
// expression being created is:
// (start of kernel code) - (start of kernel descriptor)
// It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
- Streamer.emitValue(MCBinaryExpr::createSub(
- MCSymbolRefExpr::create(
- KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
- MCSymbolRefExpr::create(
- KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
- Context),
+ Streamer.emitValue(
+ MCBinaryExpr::createSub(
+ MCSymbolRefExpr::create(KernelCodeSymbol,
+ MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
+ MCSymbolRefExpr::create(KernelDescriptorSymbol,
+ MCSymbolRefExpr::VK_None, Context),
+ Context),
sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
for (uint8_t Res : KernelDescriptor.reserved1)
Streamer.emitInt8(Res);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 6d53f68ace..1613f14d0b 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1215,8 +1215,8 @@ void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
}
}
-amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
- const MCSubtargetInfo *STI) {
+amdhsa::kernel_descriptor_t
+getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI) {
IsaVersion Version = getIsaVersion(STI->getCPU());
amdhsa::kernel_descriptor_t KD;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 29ac402d95..e7c3ca6e04 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -852,8 +852,8 @@ unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
const MCSubtargetInfo *STI);
-amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
- const MCSubtargetInfo *STI);
+amdhsa::kernel_descriptor_t
+getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI);
bool isGroupSegment(const GlobalValue *GV);
bool isGlobalSegment(const GlobalValue *GV);
``````````
</details>
https://github.com/llvm/llvm-project/pull/86151
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