[llvm] [RISCV][GISEL] Legalize, regbank select, and instruction select G_ZEXT, G_SEXT, G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP (PR #85938)

[Craig Topper via llvm-commits]

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@@ -374,6 +379,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
       .clampScalar(0, s32, sXLen)
       .lowerForCartesianProduct({s32, sXLen, p0}, {p0});
 
+  getActionDefinitionsBuilder(G_SPLAT_VECTOR)
+      .legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
+                   typeInSet(1, {s8, s16, s32, sXLen})))
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topperc wrote:

This should only be sXLen. There are no isel patterns with any other type.

https://github.com/llvm/llvm-project/pull/85938